doc: Add circuit diagram

This commit is contained in:
Markus Koch 2022-01-30 19:27:14 +01:00
parent 61812c133f
commit 5b54a596c1
2 changed files with 3047 additions and 3 deletions

View File

@ -17,10 +17,15 @@ When writing it, the following were the main design philosophies:
## Hardware
TBD. TL;DR:
![Circuit Diagram](doc/circuit.svg)
* RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL.
* TX: Meh, a series current limiting resistor is good enough.
* RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL. Also, pull up/down resistors help to avoid glitchy behavior with no cable connected or little data activity.
* TX: Meh, a series current limiting resistor is good enough. Drive two outputs differentially to increase the voltage swing. (Technically not true antivalent signals as there's also the "off" state with both disabled.)
Notes:
* The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
* On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D
## License

3039
doc/circuit.svg Normal file

File diff suppressed because it is too large Load Diff

After

Width:  |  Height:  |  Size: 229 KiB