rmii: Reset some more signals
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@ -82,7 +82,9 @@ begin
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rxp : process(rmii_rst, rmii_ref_clk) is
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rxp : process(rmii_rst, rmii_ref_clk) is
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begin
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begin
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if rmii_rst then
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if rmii_rst then
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state <= IDLE;
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state <= IDLE;
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dibit_cnt <= 0;
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sr <= (others => '0');
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elsif rising_edge(rmii_ref_clk) then
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elsif rising_edge(rmii_ref_clk) then
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-- Shift in data bytes
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-- Shift in data bytes
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@ -253,7 +255,10 @@ begin
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txp : process(rmii_ref_clk, rmii_rst) is
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txp : process(rmii_ref_clk, rmii_rst) is
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begin
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begin
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if rmii_rst then
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if rmii_rst then
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state <= IDLE;
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state <= IDLE;
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byte_cnt <= 0;
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dibit_cnt <= 0;
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sr <= (others => '-');
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elsif rising_edge(rmii_ref_clk) then
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elsif rising_edge(rmii_ref_clk) then
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sr <= "00" & sr(sr'high downto 2);
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sr <= "00" & sr(sr'high downto 2);
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@ -297,7 +302,7 @@ begin
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temp_tx_data_ack <= '1' when (state = DATA) and (byte_done = '1') and (temp_tx_data_en = '1') else '0';
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temp_tx_data_ack <= '1' when (state = DATA) and (byte_done = '1') and (temp_tx_data_en = '1') else '0';
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temp_tx_active <= '1' when state = DATA else '0';
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temp_tx_active <= '1' when state = DATA else '0';
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rmii_txd <= sr(1 downto 0);
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rmii_txd <= sr(rmii_txd'range);
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rmii_tx_en <= '1' when state = DATA else '0';
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rmii_tx_en <= '1' when state = DATA else '0';
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end block transmitter;
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end block transmitter;
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end architecture rtl;
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end architecture rtl;
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