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phy: Use byte type for ports

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This commit is contained in:
Markus Koch 2021-09-04 19:05:49 +02:00
parent 16026849e8
commit dcbd9675f6
2 changed files with 8 additions and 4 deletions
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6
trashernet/trashernet_phy.vhd
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@ -3,6 +3,8 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.trashernet_types.all;
entity trashernet_phy is
generic(
F_CLK : in integer -- Clock frequency
@ -13,11 +15,11 @@ entity trashernet_phy is
rst : in std_logic; -- Asynchronous reset
-- Eth
rx_data : out std_logic_vector(7 downto 0); -- RX Data
rx_data : out byte; -- RX Data
rx_data_valid : out std_logic; -- RX Data valid
rx_active : out std_logic; -- RX of packet in progress
tx_data : in std_logic_vector(7 downto 0); -- TX Data
tx_data : in byte; -- TX Data
tx_data_en : in std_logic; -- Transmitter enable
tx_data_ack : out std_logic; -- Latched data_tx

6
trashernet/trashernet_phy_cdc.vhd
View File

@ -2,6 +2,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.trashernet_types.all;
entity trashernet_phy_cdc is
generic(
F_CLK : in integer; -- Clock frequency of design IF
@ -14,11 +16,11 @@ entity trashernet_phy_cdc is
rst : in std_logic; -- Asynchronous reset
-- System interface
rx_data : out std_logic_vector(7 downto 0); -- RX Data
rx_data : out byte; -- RX Data
rx_data_valid : out std_logic; -- RX Data valid
rx_active : out std_logic; -- RX of packet in progress
tx_data : in std_logic_vector(7 downto 0); -- TX Data
tx_data : in byte; -- TX Data
tx_data_en : in std_logic; -- Transmitter enable
tx_data_ack : out std_logic; -- Latched data_tx