bench: Test MAC TX

bench/bench_trashernet_mac.vhd

@@ -20,10 +20,12 @@ architecture bench of bench_trashernet_mac is
 	signal tx_data        : std_logic_vector(7 downto 0);
 	signal tx_data_en     : std_logic;
 	signal tx_data_ack    : std_logic;
+	signal tx_active      : std_logic;
 	signal carrier_detect : std_logic;
 	signal rx_error       : std_logic;
 	signal rx_p           : std_logic;
 	signal tx_p           : std_logic;
+	signal tx_n           : std_logic;
 
 	signal rx_mac_destination : mac_addr_t;
 	signal rx_mac_source      : mac_addr_t;
@@ -32,6 +34,15 @@ architecture bench of bench_trashernet_mac is
 	signal rx_mac_valid       : std_logic;
 	signal rx_mac_crc_ok      : std_logic;
 	signal rx_mac_crc_error   : std_logic;
+	signal rx_mac_header_rcv  : std_logic;
+	signal tx_mac_destination : mac_addr_t;
+	signal tx_mac_source      : mac_addr_t;
+	signal tx_mac_ethertype   : ethertype_t;
+	signal tx_mac_data        : byte;
+	signal tx_mac_data_en     : std_logic;
+	signal tx_mac_data_ack    : std_logic;
+
+	constant TEST_BENCH_LOOPBACK : boolean := true;
 
 begin
 	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
@@ -49,10 +60,12 @@ begin
 			tx_data        => tx_data,
 			tx_data_en     => tx_data_en,
 			tx_data_ack    => tx_data_ack,
+			tx_active      => tx_active,
 			carrier_detect => carrier_detect,
 			rx_error       => rx_error,
 			rx_p           => rx_p,
-			tx_p           => tx_p
+			tx_p           => tx_p,
+			tx_n           => tx_n
 		);
 
 	trashernet_mac_inst : entity trashernet.trashernet_mac
@@ -65,6 +78,7 @@ begin
 			tx_data            => tx_data,
 			tx_data_en         => tx_data_en,
 			tx_data_ack        => tx_data_ack,
+			tx_active          => tx_active,
 			carrier_detect     => carrier_detect,
 			rx_error           => rx_error,
 			rx_mac_destination => rx_mac_destination,
@@ -72,8 +86,15 @@ begin
 			rx_mac_ethertype   => rx_mac_ethertype,
 			rx_mac_data        => rx_mac_data,
 			rx_mac_valid       => rx_mac_valid,
+			rx_mac_header_rcv  => rx_mac_header_rcv,
 			rx_mac_crc_ok      => rx_mac_crc_ok,
-			rx_mac_crc_error   => rx_mac_crc_error
+			rx_mac_crc_error   => rx_mac_crc_error,
+			tx_mac_destination => tx_mac_destination,
+			tx_mac_source      => tx_mac_source,
+			tx_mac_ethertype   => tx_mac_ethertype,
+			tx_mac_data        => tx_mac_data,
+			tx_mac_data_en     => tx_mac_data_en,
+			tx_mac_data_ack    => tx_mac_data_ack
 		);
 
 	clock_driver : process
@@ -94,14 +115,23 @@ begin
 		wait for period / 2;
 	end process phy_clock_driver;
 
-	test : process is
+	rstsim : process is
 	begin
-		rx_p <= '0';
-
 		rst <= '1';
 		wait for 20 ns;
 		rst <= '0';
 		wait for 20 ns;
+		wait;
+	end process rstsim;
+
+	loopbackmode : if TEST_BENCH_LOOPBACK generate
+		rx_p <= tx_p;
+	else generate
+		test : process is
+		begin
+			wait until rst = '0';
+			wait for 10 ns;
+			rx_p <= '0';
 
 			send_data(rx_p, byte_vector'(
 				x"55", x"55", x"55", x"D5",
@@ -126,6 +156,7 @@ begin
 
 			wait;
 		end process test;
+	end generate loopbackmode;
 
 	receiver : process is
 	begin
@@ -144,4 +175,25 @@ begin
 		end if;
 	end process receiver;
 
+	mac_tx : process is
+	begin
+		tx_mac_data        <= x"11";
+		tx_mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
+		tx_mac_source      <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
+		tx_mac_ethertype   <= (x"01", x"00");
+		tx_mac_data_en     <= '0';
+
+		wait until rst = '0';
+		wait for 100 ns;
+
+		tx_mac_data_en <= '1';
+		wait until rising_edge(tx_mac_data_ack);
+		wait until rising_edge(tx_mac_data_ack);
+		wait until rising_edge(tx_mac_data_ack);
+		wait until rising_edge(clk);
+		tx_mac_data_en <= '0';
+
+		wait;
+	end process mac_tx;
+
 end architecture bench;

bench/bench_trashernet_phy.vhd

@@ -24,6 +24,8 @@ architecture bench of bench_trashernet_phy is
 	signal rx_error       : std_logic;
 	signal rx_p           : std_logic;
 	signal tx_p           : std_logic;
+	signal tx_active      : std_logic;
+	signal tx_n           : std_logic;
 
 begin
 	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
@@ -41,10 +43,12 @@ begin
 			tx_data        => tx_data,
 			tx_data_en     => tx_data_en,
 			tx_data_ack    => tx_data_ack,
+			tx_active      => tx_active,
 			carrier_detect => carrier_detect,
 			rx_error       => rx_error,
 			rx_p           => rx_p,
-			tx_p           => tx_p
+			tx_p           => tx_p,
+			tx_n           => tx_n
 		);
 
 	clock_driver : process

trashernet/trashernet_mac.vhd

@@ -11,13 +11,14 @@ entity trashernet_mac is
 		rst                : in  std_logic; -- Asynchronous reset
 
 		-- PHY signals
-		rx_data            : in  std_logic_vector(7 downto 0); -- RX Data
+		rx_data            : in  byte;  -- RX Data
 		rx_data_valid      : in  std_logic; -- RX Data valid
 		rx_active          : in  std_logic; -- RX of packet in progress
 
-		tx_data            : out std_logic_vector(7 downto 0); -- TX Data
+		tx_data            : out byte;  -- TX Data
 		tx_data_en         : out std_logic; -- Transmitter enable
 		tx_data_ack        : in  std_logic; -- Latched data_tx
+		tx_active          : in  std_logic; -- Transmitter active
 
 		carrier_detect     : in  std_logic; -- Carrier detected
 		rx_error           : in  std_logic; -- Receive error
@@ -30,14 +31,19 @@ entity trashernet_mac is
 		rx_mac_valid       : out std_logic; -- `rx_mac` values (headers + data) are valid
 		rx_mac_header_rcv  : out std_logic; -- `rx_mac` header have been received and are valid
 		rx_mac_crc_ok      : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
-		rx_mac_crc_error   : out std_logic -- End of packet, CRC invalid
+		rx_mac_crc_error   : out std_logic; -- End of packet, CRC invalid
+
+		tx_mac_destination : in  mac_addr_t; -- Destination MAC address 
+		tx_mac_source      : in  mac_addr_t; -- Source MAC address
+		tx_mac_ethertype   : in  ethertype_t; -- Ethertype or length
+		tx_mac_data        : in  byte;  -- Payload
+		tx_mac_data_en     : in  std_logic; -- Start (and keep) transmitting a frame
+		tx_mac_data_ack    : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word.
 	);
 end entity trashernet_mac;
 
 architecture rtl of trashernet_mac is
-	signal crc       : std_logic_vector(31 downto 0);
+	constant ETH_POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7";
-	signal crc_ok    : std_logic;
-	signal crc_clear : std_logic;
 
 begin
 	rx : block
@@ -52,7 +58,9 @@ begin
 
 		signal sr_payload : byte_vector(0 to 4);
 
-		constant ETH_POLYNOMIAL : std_logic_vector(crc'range) := x"04C11DB7";
+		signal crc       : std_logic_vector(ETH_POLYNOMIAL'range);
+		signal crc_ok    : std_logic;
+		signal crc_clear : std_logic;
 	begin
 		crc_inst : entity work.crc
 			generic map(
@@ -136,4 +144,88 @@ begin
 
 	end block rx;
 
+	tx : block
+		type tx_state_t is (IDLE, HEADER, DATA, TXCRC);
+		signal tx_state : tx_state_t;
+
+		signal sr            : byte_vector(0 to tx_mac_destination'length + tx_mac_source'length + tx_mac_ethertype'length - 1);
+		constant BIT_CNT_MAX : integer := sr'high;
+		signal byte_cnt      : integer range 0 to BIT_CNT_MAX;
+
+		signal crc       : std_logic_vector(ETH_POLYNOMIAL'range);
+		signal crc_clear : std_logic;
+		signal crc_valid : std_logic;
+	begin
+		crc_inst : entity work.crc
+			generic map(
+				POLYNOMIAL  => ETH_POLYNOMIAL,
+				START       => x"FFFFFFFF",
+				FINAL_XOR   => x"FFFFFFFF",
+				REVERSE_OUT => true
+			)
+			port map(
+				clk        => clk,
+				rst        => rst,
+				data       => tx_data,
+				data_valid => crc_valid,
+				crc_clear  => crc_clear,
+				crc_out    => crc
+			);
+
+		tx_main : process(clk, rst) is
+		begin
+			if rst then
+				tx_mac_data_ack <= '0';
+
+			elsif rising_edge(clk) then
+				tx_mac_data_ack <= '0';
+				crc_valid       <= '0';
+
+				if tx_data_ack then
+					sr        <= sr(sr'low + 1 to sr'high) & x"00";
+					crc_valid <= '1';
+					if byte_cnt /= 0 then
+						byte_cnt <= byte_cnt - 1;
+					end if;
+				end if;
+				case tx_state is
+					when IDLE =>
+						if not tx_active and tx_mac_data_en then
+							sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
+							byte_cnt   <= 7;
+							tx_state   <= HEADER;
+						end if;
+
+					when HEADER =>
+						if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
+							sr        <= tx_mac_destination & tx_mac_source & tx_mac_ethertype;
+							crc_valid <= '1';
+							byte_cnt  <= BIT_CNT_MAX;
+							tx_state  <= DATA;
+						end if;
+
+					when DATA =>
+						if (tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete
+							if tx_mac_data_en then
+								sr(0)           <= tx_mac_data;
+								tx_mac_data_ack <= '1';
+							else
+								sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24));
+								byte_cnt   <= 4 - 1;
+								tx_state   <= TXCRC;
+							end if;
+						end if;
+
+					when TXCRC =>
+						if (tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete
+							tx_state <= IDLE;
+						end if;
+				end case;
+			end if;
+		end process tx_main;
+		tx_data_en <= '1' when tx_state /= IDLE else '0';
+		crc_clear  <= '1' when tx_state = HEADER else '0';
+		tx_data    <= sr(sr'low);
+	end block tx;
+
 end architecture rtl;

trashernet/trashernet_phy.vhd

@@ -3,6 +3,8 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.math_real.all;
 
+use work.trashernet_types.all;
+
 entity trashernet_phy is
 	generic(
 		F_CLK : in integer              -- Clock frequency
@@ -13,13 +15,14 @@ entity trashernet_phy is
 		rst            : in  std_logic; -- Asynchronous reset
 
 		-- Eth
-		rx_data        : out std_logic_vector(7 downto 0); -- RX Data
+		rx_data        : out byte;      -- RX Data
 		rx_data_valid  : out std_logic; -- RX Data valid
 		rx_active      : out std_logic; -- RX of packet in progress
 
-		tx_data        : in  std_logic_vector(7 downto 0); -- TX Data
+		tx_data        : in  byte;      -- TX Data
 		tx_data_en     : in  std_logic; -- Transmitter enable
 		tx_data_ack    : out std_logic; -- Latched data_tx
+		tx_active      : out std_logic; -- Transmission in progress
 
 		carrier_detect : out std_logic; -- Carrier detected
 		rx_error       : out std_logic; -- Receive error
@@ -280,7 +283,7 @@ begin
 				sr          <= tx_data;
 				bit_stage   <= '0';
 				bit_cnt     <= BIT_CNT_MAX_DATA;
-				tx_data_ack <= '0';
+				tx_data_ack <= '1';
 			end procedure transmit_byte;
 
 			procedure transmit_ipg is
@@ -339,6 +342,7 @@ begin
 					when IDLE =>
 						if tx_data_en then -- New packet to TX
 							transmit_byte;
+							bit_stage  <= '1';
 							tx_stb_cnt <= TX_STB_CNT_MAX; -- resync
 
 						elsif bit_cnt = 0 then -- NLP timeout
@@ -372,6 +376,7 @@ begin
 				end case;
 			end if;
 		end process tx_main;
+		tx_active <= '1' when tx_state /= IDLE else '0';
 
 		driver : process(clk, rst) is
 		begin

trashernet/trashernet_phy_cdc.vhd

@@ -2,6 +2,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+use work.trashernet_types.all;
+
 entity trashernet_phy_cdc is
 	generic(
 		F_CLK     : in integer;         -- Clock frequency of design IF
@@ -14,20 +16,22 @@ entity trashernet_phy_cdc is
 		rst            : in  std_logic; -- Asynchronous reset
 
 		-- System interface
-		rx_data        : out std_logic_vector(7 downto 0); -- RX Data
+		rx_data        : out byte; -- RX Data
 		rx_data_valid  : out std_logic; -- RX Data valid
 		rx_active      : out std_logic; -- RX of packet in progress
 
-		tx_data        : in  std_logic_vector(7 downto 0); -- TX Data
+		tx_data        : in  byte; -- TX Data
 		tx_data_en     : in  std_logic; -- Transmitter enable
 		tx_data_ack    : out std_logic; -- Latched data_tx
+		tx_active      : out std_logic; -- Transmission in progress
 
 		carrier_detect : out std_logic; -- Carrier detected
 		rx_error       : out std_logic; -- Receive error
 
 		-- Ethernet physical signals
 		rx_p           : in  std_logic;
-		tx_p           : out std_logic
+		tx_p           : out std_logic;
+		tx_n           : out std_logic
 	);
 end entity trashernet_phy_cdc;
 
@@ -42,6 +46,7 @@ architecture RTL of trashernet_phy_cdc is
 	signal phy_tx_data_ack    : std_logic;
 	signal phy_carrier_detect : std_logic;
 	signal phy_rx_error       : std_logic;
+	signal phy_tx_active      : std_logic;
 
 	-- Helper signals
 	signal rx_data_valid_i : std_logic;
@@ -72,10 +77,12 @@ begin
 			tx_data        => phy_tx_data,
 			tx_data_en     => phy_tx_data_en,
 			tx_data_ack    => phy_tx_data_ack,
+			tx_active      => phy_tx_active,
 			carrier_detect => phy_carrier_detect,
 			rx_error       => phy_rx_error,
 			rx_p           => rx_p,
-			tx_p           => tx_p
+			tx_p           => tx_p,
+			tx_n           => tx_n
 		);
 
 	synchronizer_txen_inst : entity work.synchronizer
@@ -150,4 +157,12 @@ begin
 			data_out => carrier_detect
 		);
 
+	synchronizer_txa_inst : entity work.synchronizer
+		port map(
+			clk      => clk,
+			rst      => rst,
+			data_in  => phy_tx_active,
+			data_out => tx_active
+		);
+
 end architecture RTL;