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3 changed files with 10 additions and 4 deletions

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@ -6,7 +6,7 @@ BASE = $(PWD)/..
BENCHTOP ?= cocotb_top_mac_test
COMPILE_ARGS=--std=08
SIM_ARGS ?= --wave=wave.ghw
# SIM_ARGS ?= --wave=wave.ghw
VHDL_SOURCES_trashernet += $(BASE)/trashernet/*.vhd
VHDL_SOURCES_design += $(BASE)/design/*.vhd

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@ -50,6 +50,7 @@ class MacDevReceiver():
if len(r) < 60:
r += b'\x00' * (60 - len(r))
r += self.eth_fcs(r)
self.dut._log.debug("DUT RX: " + str(r))
await self.eth_tx.send(ETH_HEAD + r);
except:
await Timer(1, "us")
@ -64,7 +65,7 @@ class MacDevReceiver():
except:
self.dut._log.debug("NLP / Invalid frame")
continue
self.dut._log.info("RX Frame: " + str(frame))
self.dut._log.debug("DUT TX: " + str(frame))
self.macdev.send(frame)
async def start(self):

View File

@ -124,7 +124,7 @@ begin
elsif rising_edge(clk) then
case state is
when IDLE =>
if mac_out.tx_active then
if not mac_out.tx_active then
if (ethernet_i_in.tx_en) then -- ETH I has priority
sel <= SEL_ETH_I;
state <= TXD;
@ -140,13 +140,18 @@ begin
end if;
when TXD =>
state <= IDLE when (mac_in.tx_mac_data_en or mac_out.tx_active);
state <= IDLE when (mac_in.tx_mac_data_en or not mac_out.tx_active);
end case;
end if;
end process arb;
mux : process(all) is
begin
-- Defaults to avoid latch
tx_data_ack_i <= '0';
tx_data_ack_ii <= (others => '0');
-- Actual MUX
if (sel = SEL_ETH_I) then
mac_in.tx_mac_data_en <= ethernet_i_in.tx_en;
mac_in.tx_mac_data <= ethernet_i_in.tx_data;