Markus Koch markus
markus pushed to feature/fpga at electronics/trashernet-soc 2024-08-09 11:28:50 +02:00
b06ccdda2a fpga: Update UART baud rate to 250 kbaud/s
876693ca5f fpga: uart_wb: Latch received byte to allow late retrieval of data
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markus pushed to feature/fpga at electronics/trashernet-soc 2024-08-07 17:58:21 +02:00
e561c31691 sw: bootrom: Improve performance and reduce size
markus pushed to feature/fpga at electronics/trashernet-soc 2024-08-01 21:09:12 +02:00
49ccbea9e9 fpga: aps6404l device model: Remove unnecessary newlines
markus pushed to feature/fpga at electronics/trashernet-soc 2024-08-01 21:08:23 +02:00
eddbcf5f6f fpga: trashernet_phy_wb: Ensure LEDs blink even with constant traffic
74280fb79a fpga: Implement single-instruction prefetching from external RAM
280b354813 fpga: aps6404l_controller: Add generic to select wrap mode
7bece90229 fpga: Cleanly separate build VUnit from bench VUnit
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markus pushed to feature/fpga at electronics/trashernet-soc 2024-07-26 10:53:31 +02:00
db5a14a2f0 fpga: Add generic FIFO core
markus pushed to feature/fpga at electronics/trashernet-soc 2024-07-23 19:11:57 +02:00
e81166a82c fpga: Implement functional Ethernet controller
markus pushed to feature/fpga at electronics/trashernet-soc 2024-07-23 19:08:58 +02:00
f0f9a1953b fpga: Implement functional Ethernet controller
79b1153df7 env: Makefile: Add support for icetime
0209a23980 fpga: Fix clock constraint for system clock
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markus pushed to feature/trashernet-soc at fpga/trashernet 2024-07-23 19:00:19 +02:00
206332f3d1 raw_mac: Implement MAC without header field en-/decoding (only CRC + framing)
markus pushed to master at fpga/trashernet 2024-07-15 13:36:50 +02:00
7379df7b74 phy: Improve clock accuracy at 0.5 dividers at the cost of some jitter
markus created branch feature/trashernet-soc in fpga/trashernet 2024-07-15 13:36:42 +02:00
markus pushed to feature/trashernet-soc at fpga/trashernet 2024-07-15 13:36:42 +02:00
f57b0b1054 raw_mac: Implement MAC without header field en-/decoding (only CRC + framing)
7379df7b74 phy: Improve clock accuracy at 0.5 dividers at the cost of some jitter
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markus pushed to master at electronics/trashernet-soc 2024-07-07 20:08:40 +02:00
263f9c566a kicad: Fix XO frequency and flash power
markus pushed to feature/fpga at electronics/trashernet-soc 2024-07-07 15:58:09 +02:00
23c7d0ab20 env: run.py: Remove unnecessary files from compilation for synthesis
markus pushed to feature/fpga at electronics/trashernet-soc 2024-07-07 15:34:45 +02:00
07bac62438 tools: Add flash.py
markus pushed to feature/fpga at electronics/trashernet-soc 2024-07-07 15:31:18 +02:00
e1672bb712 fpga: Test Trashernet TX
markus pushed to feature/fpga at electronics/trashernet-soc 2024-07-06 19:15:22 +02:00
4057f5239e sw: Add bootrom
434a06fa70 env: Replace build script with proper Makefile
dd7cf08b6f fpga: Continue work on full HW support
c7caf2189b doc: Add a copy of the MPL-2.0
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markus pushed to master at fpga/trashernet 2024-07-06 18:04:41 +02:00
21a0d0e69a phy_cdc: Allow unlimited clock ratios
943febcb99 phy_cdc: Fix synchronization behavior
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markus pushed to feature/fpga at electronics/trashernet-soc 2024-06-22 11:24:06 +02:00
b7c1286d76 fpga: Implement basic SERV SoC
markus pushed to feature/fpga at electronics/trashernet-soc 2024-06-22 11:23:27 +02:00
262a979ec3 fpga: Implement basic SERV SoC
markus pushed to feature/fpga at electronics/trashernet-soc 2024-06-22 11:18:36 +02:00
e333a3d0d6 fpga: Implement basic SERV SoC