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e561c31691
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sw: bootrom: Improve performance and reduce size
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2024-08-07 18:01:22 +02:00 |
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49ccbea9e9
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fpga: aps6404l device model: Remove unnecessary newlines
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2024-08-01 21:11:47 +02:00 |
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eddbcf5f6f
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fpga: trashernet_phy_wb: Ensure LEDs blink even with constant traffic
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2024-08-01 21:10:53 +02:00 |
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74280fb79a
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fpga: Implement single-instruction prefetching from external RAM
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2024-08-01 21:06:14 +02:00 |
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280b354813
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fpga: aps6404l_controller: Add generic to select wrap mode
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2024-08-01 21:03:12 +02:00 |
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7bece90229
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fpga: Cleanly separate build VUnit from bench VUnit
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2024-08-01 21:02:32 +02:00 |
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db5a14a2f0
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fpga: Add generic FIFO core
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2024-07-26 10:55:32 +02:00 |
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e81166a82c
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fpga: Implement functional Ethernet controller
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2024-07-23 19:13:42 +02:00 |
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79b1153df7
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env: Makefile: Add support for icetime
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2024-07-23 18:53:17 +02:00 |
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0209a23980
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fpga: Fix clock constraint for system clock
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2024-07-23 18:52:14 +02:00 |
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23c7d0ab20
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env: run.py: Remove unnecessary files from compilation for synthesis
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2024-07-07 15:58:32 +02:00 |
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07bac62438
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tools: Add flash.py
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2024-07-07 15:35:09 +02:00 |
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e1672bb712
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fpga: Test Trashernet TX
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2024-07-07 15:31:41 +02:00 |
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4057f5239e
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sw: Add bootrom
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2024-07-06 19:15:41 +02:00 |
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434a06fa70
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env: Replace build script with proper Makefile
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2024-07-06 19:15:20 +02:00 |
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dd7cf08b6f
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fpga: Continue work on full HW support
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2024-07-06 19:14:39 +02:00 |
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c7caf2189b
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doc: Add a copy of the MPL-2.0
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2024-07-06 19:06:39 +02:00 |
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b7c1286d76
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fpga: Implement basic SERV SoC
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2024-06-22 11:28:15 +02:00 |
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79c466ec50
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Add licensing information
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2024-06-02 10:30:26 +02:00 |
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2f54996271
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Swap RX+ and -
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2024-06-02 10:15:13 +02:00 |
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bdeff0d0ff
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Design PCB
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2024-06-01 12:23:16 +02:00 |
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