|  | e81166a82c | fpga: Implement functional Ethernet controller | 2024-07-23 19:13:42 +02:00 |  | 
			
				
					|  | 79b1153df7 | env: Makefile: Add support for icetime | 2024-07-23 18:53:17 +02:00 |  | 
			
				
					|  | 0209a23980 | fpga: Fix clock constraint for system clock | 2024-07-23 18:52:14 +02:00 |  | 
			
				
					|  | 23c7d0ab20 | env: run.py: Remove unnecessary files from compilation for synthesis | 2024-07-07 15:58:32 +02:00 |  | 
			
				
					|  | 07bac62438 | tools: Add flash.py | 2024-07-07 15:35:09 +02:00 |  | 
			
				
					|  | e1672bb712 | fpga: Test Trashernet TX | 2024-07-07 15:31:41 +02:00 |  | 
			
				
					|  | 4057f5239e | sw: Add bootrom | 2024-07-06 19:15:41 +02:00 |  | 
			
				
					|  | 434a06fa70 | env: Replace build script with proper Makefile | 2024-07-06 19:15:20 +02:00 |  | 
			
				
					|  | dd7cf08b6f | fpga: Continue work on full HW support | 2024-07-06 19:14:39 +02:00 |  | 
			
				
					|  | c7caf2189b | doc: Add a copy of the MPL-2.0 | 2024-07-06 19:06:39 +02:00 |  | 
			
				
					|  | b7c1286d76 | fpga: Implement basic SERV SoC | 2024-06-22 11:28:15 +02:00 |  | 
			
				
					|  | 79c466ec50 | Add licensing information | 2024-06-02 10:30:26 +02:00 |  | 
			
				
					|  | 2f54996271 | Swap RX+ and -
						
						
						
						
						
						
							
 rev-1.0 | 2024-06-02 10:15:13 +02:00 |  | 
			
				
					|  | bdeff0d0ff | Design PCB | 2024-06-01 12:23:16 +02:00 |  |