trashernet-soc/fpga/hdl
Markus Koch 876693ca5f fpga: uart_wb: Latch received byte to allow late retrieval of data
Else, the CPU would get the part old / half current byte. This
enables boot loader baud rates in excess of 19200 baud.
2024-08-09 11:29:33 +02:00
..
bench fpga: Implement single-instruction prefetching from external RAM 2024-08-01 21:06:14 +02:00
design fpga: uart_wb: Latch received byte to allow late retrieval of data 2024-08-09 11:29:33 +02:00
device_models fpga: aps6404l device model: Remove unnecessary newlines 2024-08-01 21:11:47 +02:00
generics fpga: Add generic FIFO core 2024-07-26 10:55:32 +02:00
serv@086090046c fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00
trashernet@206332f3d1 fpga: Implement functional Ethernet controller 2024-07-23 19:13:42 +02:00
header.sh fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00