trashernet-soc/fpga/hdl/design
Markus Koch 876693ca5f fpga: uart_wb: Latch received byte to allow late retrieval of data
Else, the CPU would get the part old / half current byte. This
enables boot loader baud rates in excess of 19200 baud.
2024-08-09 11:29:33 +02:00
..
aps6404l_controller.vhd fpga: aps6404l_controller: Add generic to select wrap mode 2024-08-01 21:03:12 +02:00
aps6404l_wb.vhd fpga: Implement single-instruction prefetching from external RAM 2024-08-01 21:06:14 +02:00
pll0.vhd fpga: Continue work on full HW support 2024-07-06 19:14:39 +02:00
serv_top_vhdl.vhd fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00
servant_gpio_vhdl.vhd fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00
servant_ram.vhd fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00
servant_timer_vhdl.vhd fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00
top.vhd fpga: Implement single-instruction prefetching from external RAM 2024-08-01 21:06:14 +02:00
trashernet_phy_wb.vhd fpga: trashernet_phy_wb: Ensure LEDs blink even with constant traffic 2024-08-01 21:10:53 +02:00
uart_wb.vhd fpga: uart_wb: Latch received byte to allow late retrieval of data 2024-08-09 11:29:33 +02:00