Commit Graph

30 Commits (master)

Author SHA1 Message Date
Markus Koch 6d28c3152c Added license info 2017-03-17 22:10:27 +01:00
Markus Koch 34d5aadf0c Bootrom, icache, bugfixes, ... 2017-03-02 22:22:43 +01:00
Markus Koch af2cad643b Bugfix in WB-AVL converter; it now accepts WB transactions with no STB inactive cycle 2017-03-02 12:19:04 +01:00
Markus Koch 2ad42a9664 Removed SRAM from top level 2017-03-02 12:18:20 +01:00
Markus Koch 3fffa6efe3 Added address masking to crossbar switch 2017-03-02 09:31:05 +01:00
Markus Koch 20387479c0 Added UART to top level 2017-03-02 09:30:38 +01:00
Markus Koch 4ca1ba0928 Converted UART to Wishbone v3 2017-03-02 09:29:41 +01:00
Markus Koch 32434cf802 previously forgot to commit fancy_spi_master 2017-03-02 08:52:09 +01:00
Markus Koch 76e6217642 Added prelim. GPIO 2017-03-02 08:51:53 +01:00
Markus Koch 2eacd7041d Added in_simulation flag to DDR3 init to allow starting (crippled) sim 2017-03-02 08:00:41 +01:00
Markus Koch c649c073ce Rewrote SPI PHY -> Flash ROM works now 2017-03-01 19:08:01 +01:00
Markus Koch b48571db24 Extended top test bench 2017-02-26 20:40:29 +01:00
Markus Koch dfcd35b152 Added Flashrom to top level 2017-02-26 20:39:51 +01:00
Markus Koch cbda2c1302 Corrected bit count for readpage (now works on real HW) 2017-02-26 20:38:29 +01:00
Markus Koch d3b2ea88b5 Fixed bug in flashrom_spi causing the clock to be active for too long 2017-02-26 18:30:25 +01:00
Markus Koch bf1e95a576 Added ID defines to crossbar 2017-02-26 16:26:06 +01:00
Markus Koch d33b027e28 Added CS inactive delay + some other fixes 2017-02-26 15:13:19 +01:00
Markus Koch e053da3ae1 flashrom: Added Wishbone controller 2016-12-10 20:51:00 +01:00
Markus Koch 9051e3385b flashrom: Minor changes 2016-12-10 20:50:03 +01:00
Markus Koch 054ae0e210 flashrom: Added wait-not-busy after write 2016-12-06 21:24:09 +01:00
Markus Koch 265d1a80e1 flashrom: Added write command, fixed read command 2016-12-06 19:53:39 +01:00
Markus Koch f55d735855 flashrom: Changed read count 2016-12-06 16:47:31 +01:00
Markus Koch c38d926569 Added page read (incomplete) 2016-12-05 20:37:04 +01:00
Markus Koch 202df5380b flashrom: Added code to enforce a cs inactive delay between SPI transactions 2016-12-05 20:35:35 +01:00
Markus Koch 9ff7421242 flashrom: Cleanup 2016-12-04 18:27:58 +01:00
Markus Koch 5ad7677b3a flashrom: Added GETSTATUS command 2016-12-04 18:00:31 +01:00
Markus Koch e66c98a670 flashrom: Transmitted one clock cycle too long -> buffer shifted 2016-12-04 17:58:27 +01:00
Markus Koch b01f74648e dataflash-model: some reformatting and removed timing checks 2016-08-04 21:00:36 +02:00
Markus Koch 9b379e70fe flashrom: Changed SPI core to conform to DataFlash behavior, changed main fsm to request the right number of transactions 2016-08-04 20:59:43 +02:00
Markus Koch a1efcf62c4 Initial commit 2016-08-04 19:22:38 +02:00