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6d28c3152c
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Added license info
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2017-03-17 22:10:27 +01:00 |
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34d5aadf0c
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Bootrom, icache, bugfixes, ...
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2017-03-02 22:22:43 +01:00 |
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af2cad643b
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Bugfix in WB-AVL converter; it now accepts WB transactions with no STB inactive cycle
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2017-03-02 12:19:04 +01:00 |
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2ad42a9664
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Removed SRAM from top level
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2017-03-02 12:18:20 +01:00 |
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3fffa6efe3
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Added address masking to crossbar switch
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2017-03-02 09:31:05 +01:00 |
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20387479c0
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Added UART to top level
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2017-03-02 09:30:38 +01:00 |
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4ca1ba0928
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Converted UART to Wishbone v3
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2017-03-02 09:29:41 +01:00 |
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32434cf802
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previously forgot to commit fancy_spi_master
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2017-03-02 08:52:09 +01:00 |
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76e6217642
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Added prelim. GPIO
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2017-03-02 08:51:53 +01:00 |
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2eacd7041d
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Added in_simulation flag to DDR3 init to allow starting (crippled) sim
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2017-03-02 08:00:41 +01:00 |
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c649c073ce
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Rewrote SPI PHY -> Flash ROM works now
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2017-03-01 19:08:01 +01:00 |
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b48571db24
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Extended top test bench
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2017-02-26 20:40:29 +01:00 |
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dfcd35b152
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Added Flashrom to top level
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2017-02-26 20:39:51 +01:00 |
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cbda2c1302
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Corrected bit count for readpage (now works on real HW)
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2017-02-26 20:38:29 +01:00 |
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d3b2ea88b5
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Fixed bug in flashrom_spi causing the clock to be active for too long
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2017-02-26 18:30:25 +01:00 |
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bf1e95a576
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Added ID defines to crossbar
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2017-02-26 16:26:06 +01:00 |
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d33b027e28
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Added CS inactive delay + some other fixes
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2017-02-26 15:13:19 +01:00 |
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e053da3ae1
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flashrom: Added Wishbone controller
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2016-12-10 20:51:00 +01:00 |
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9051e3385b
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flashrom: Minor changes
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2016-12-10 20:50:03 +01:00 |
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054ae0e210
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flashrom: Added wait-not-busy after write
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2016-12-06 21:24:09 +01:00 |
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265d1a80e1
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flashrom: Added write command, fixed read command
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2016-12-06 19:53:39 +01:00 |
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f55d735855
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flashrom: Changed read count
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2016-12-06 16:47:31 +01:00 |
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c38d926569
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Added page read (incomplete)
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2016-12-05 20:37:04 +01:00 |
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202df5380b
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flashrom: Added code to enforce a cs inactive delay between SPI transactions
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2016-12-05 20:35:35 +01:00 |
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9ff7421242
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flashrom: Cleanup
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2016-12-04 18:27:58 +01:00 |
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5ad7677b3a
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flashrom: Added GETSTATUS command
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2016-12-04 18:00:31 +01:00 |
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e66c98a670
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flashrom: Transmitted one clock cycle too long -> buffer shifted
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2016-12-04 17:58:27 +01:00 |
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b01f74648e
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dataflash-model: some reformatting and removed timing checks
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2016-08-04 21:00:36 +02:00 |
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9b379e70fe
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flashrom: Changed SPI core to conform to DataFlash behavior, changed main fsm to request the right number of transactions
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2016-08-04 20:59:43 +02:00 |
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a1efcf62c4
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Initial commit
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2016-08-04 19:22:38 +02:00 |
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