fpga/trashernet
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Code Issues 7 Pull Requests 2 Releases 2 Wiki Activity

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base: fpga:7c49812bdfe2be66d5b2758396cbe40e9f4933c5
Branches Tags
fpga:master
fpga:feature/trashernet-soc
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1
..
compare: fpga:3c1c14f9531d4218454e220b36d4424f0c8e673e
Branches Tags
fpga:feature/trashernet-soc
fpga:master
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1

4 Commits
7c49812bdf ... 3c1c14f953

Author SHA1 Message Date
Markus Koch
3c1c14f953 bench: hw_itl: Add debug prints for RX/TX 2022-05-15 14:37:21 +02:00
Markus Koch
50b65bccec eth: tx: Remove accidental latch 2022-05-15 14:30:45 +02:00
Markus Koch
461c7ebce1 eth: tx: Fix polarity of tx_active checks 2022-05-15 14:27:26 +02:00
Markus Koch
eab8783c6b bench: Disable wave logging by default 2022-05-13 21:03:12 +02:00
2 changed files with 9 additions and 3 deletions
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3
cocotb/hw_itl.py
View File

@ -50,6 +50,7 @@ class MacDevReceiver():
if len(r) < 60: if len(r) < 60:
r += b'\x00' * (60 - len(r)) r += b'\x00' * (60 - len(r))
r += self.eth_fcs(r) r += self.eth_fcs(r)
self.dut._log.debug("DUT RX: " + str(r))
await self.eth_tx.send(ETH_HEAD + r); await self.eth_tx.send(ETH_HEAD + r);
except: except:
await Timer(1, "us") await Timer(1, "us")
@ -64,7 +65,7 @@ class MacDevReceiver():
except: except:
self.dut._log.debug("NLP / Invalid frame") self.dut._log.debug("NLP / Invalid frame")
continue continue
self.dut._log.info("RX Frame: " + str(frame)) self.dut._log.debug("DUT TX: " + str(frame))
self.macdev.send(frame) self.macdev.send(frame)
async def start(self): async def start(self):

9
trashernet/trashernet_eth.vhd
View File

@ -124,7 +124,7 @@ begin
elsif rising_edge(clk) then elsif rising_edge(clk) then
case state is case state is
when IDLE => when IDLE =>
if mac_out.tx_active then if not mac_out.tx_active then
if (ethernet_i_in.tx_en) then -- ETH I has priority if (ethernet_i_in.tx_en) then -- ETH I has priority
sel <= SEL_ETH_I; sel <= SEL_ETH_I;
state <= TXD; state <= TXD;
@ -140,13 +140,18 @@ begin
end if; end if;
when TXD => when TXD =>
state <= IDLE when (mac_in.tx_mac_data_en or mac_out.tx_active); state <= IDLE when (mac_in.tx_mac_data_en or not mac_out.tx_active);
end case; end case;
end if; end if;
end process arb; end process arb;
mux : process(all) is mux : process(all) is
begin begin
-- Defaults to avoid latch
tx_data_ack_i <= '0';
tx_data_ack_ii <= (others => '0');
-- Actual MUX
if (sel = SEL_ETH_I) then if (sel = SEL_ETH_I) then
mac_in.tx_mac_data_en <= ethernet_i_in.tx_en; mac_in.tx_mac_data_en <= ethernet_i_in.tx_en;
mac_in.tx_mac_data <= ethernet_i_in.tx_data; mac_in.tx_mac_data <= ethernet_i_in.tx_data;