Block a user
PHY:TX: Improve handling of NLP timing generation
RX Data
Hmmm maybe instead of the pull-up, we can do implement a better link-detection in the FPGA... I don't want to affect the input impedance etc...
DEMO: Implement MAC-layer test design
PHY:TX: Improve handling of NLP timing generation
a9039a175c
phy+mac: Improve interface
4a39c3d638
phy: Notify that the end-of-packet has been accepted
d1150fb7db
demo: Add MAC demo design
d1e0143c9d
phy: Fix TX manchester encoding
1bcddf4273
phy: Improve NLP timeout accuracy
a9039a175c
phy+mac: Improve interface
4a39c3d638
phy: Notify that the end-of-packet has been accepted
d1150fb7db
demo: Add MAC demo design
d1e0143c9d
phy: Fix TX manchester encoding
1bcddf4273
phy: Improve NLP timeout accuracy
DEMO: Implement MAC-layer test design
RX works pretty much flawlessly in afb545cd021961aee6f4d66259116d194454465e, TX proves to be a little more difficult... not sure why yet, might be a HW issue.
afb545cd02
Clean up code formatting
4e39e3b371
phy: Do not report tx_active when providing NLPs
a2edc540b2
phy: Fix NLP timebase error
6f8bb7ba54
phy: Fix rounding error for NLP timeout
76eaff20fd
mac+phy: Initialize all required variables