Markus Koch

markus pushed to sw at electronics/ttl-fpga

2019-09-22 19:10:14 +02:00

f27c728472 sw: Implement bodgefix for schematic rev 03L

30c83a658f sw: Fix fpga_cell_lut34_lut_get_out_mux

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markus commented on issue electronics/ttl-fpga#12

2019-09-22 18:20:04 +02:00

LUT output-muxing pin-swap

Updated schematic to include bodge-fix in commit 4424d762f795f9c86a4c5bc972bd4f7345903f07.

markus pushed to master at electronics/ttl-fpga

2019-09-22 18:19:13 +02:00

4424d762f7 kicad: Update kicad_pcb schematic to include bodge-fixes

markus commented on issue electronics/ttl-fpga#12

2019-09-22 17:58:34 +02:00

LUT output-muxing pin-swap

The only real solution is to Cut U7 pin 12 (B), connect to 13 (A) for the upper LUT, and then modify LUT-2 to use a_async. This should give us true full flexibility. But this is more than just shorting two pins, so for the current rev I'll go with the following:

markus commented on issue electronics/ttl-fpga#12

2019-09-22 17:57:05 +02:00

LUT output-muxing pin-swap

Another idea: Cut U7 pin 12 (B), connect to 13 (A). Cut U10 pin 13 (A), connect to 12 (B).

markus pushed to sw at electronics/ttl-fpga

2019-09-13 08:08:14 +02:00

0a493bdd2a Remove unnecessary debug output

a072dbfe8a Fix unnecessary semicolon warnings in bit set / unset macros

a2abccfc5d Fix output MUX selection logic

7abcead6a9 des: Fix data type of drive_sel

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markus closed issue electronics/ttl-fpga#15

2019-09-13 08:08:13 +02:00

Output MUX selection only allows first pair

markus opened issue electronics/ttl-fpga#15

2019-09-13 05:55:22 +02:00

Output MUX selection only allows first pair