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electronics/trashernet-soc
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16 Commits 3 Branches 1 Tag
Commit Graph

10 Commits

Author SHA1 Message Date
Markus Koch
7bece90229 fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
Markus Koch
db5a14a2f0 fpga: Add generic FIFO core 2024-07-26 10:55:32 +02:00
Markus Koch
e81166a82c fpga: Implement functional Ethernet controller 2024-07-23 19:13:42 +02:00
Markus Koch
79b1153df7 env: Makefile: Add support for icetime 2024-07-23 18:53:17 +02:00
Markus Koch
0209a23980 fpga: Fix clock constraint for system clock 2024-07-23 18:52:14 +02:00
Markus Koch
23c7d0ab20 env: run.py: Remove unnecessary files from compilation for synthesis 2024-07-07 15:58:32 +02:00
Markus Koch
e1672bb712 fpga: Test Trashernet TX 2024-07-07 15:31:41 +02:00
Markus Koch
434a06fa70 env: Replace build script with proper Makefile 2024-07-06 19:15:20 +02:00
Markus Koch
dd7cf08b6f fpga: Continue work on full HW support 2024-07-06 19:14:39 +02:00
Markus Koch
b7c1286d76 fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00
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