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b8f273c9b6
Author | SHA1 | Date | |
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b8f273c9b6 | |||
9487f5c2ef | |||
f21122c54b | |||
0943656548 | |||
4ca35ca18c | |||
539d2e0908 |
@ -46,6 +46,7 @@ $(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
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# Collect GHDL sources from VUnit
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# Collect GHDL sources from VUnit
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$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
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$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
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yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
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yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
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./patch_asserts.sh $@
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$(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
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$(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
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nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)
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nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)
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181
fpga/hdl/bench/bench_top_zephyr.vhd
Normal file
181
fpga/hdl/bench/bench_top_zephyr.vhd
Normal file
@ -0,0 +1,181 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- Inspection-only test bench to run a larger memory image from external RAM.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library design;
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use design.all;
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library generics;
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use generics.wishbone_pkg.all;
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library device_models;
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use device_models.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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library osvvm;
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context osvvm.osvvmContext;
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use osvvm.ScoreboardPkg_slv.all;
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entity bench_top_zephyr is
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generic(
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runner_cfg : string := runner_cfg_default
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);
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end entity bench_top_zephyr;
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architecture RTL of bench_top_zephyr is
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constant UART_BAUD : integer := 250000;
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signal clk_in : std_logic;
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signal uart_tx : std_logic;
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signal uart_rx : std_logic;
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signal eth_rx_p : std_logic;
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signal eth_tx_p : std_logic_vector(3 downto 0);
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signal eth_tx_n : std_logic_vector(3 downto 0);
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signal eth_led_green_n : std_logic;
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signal eth_led_orange_n : std_logic;
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signal led_user : std_logic;
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signal psram_ce_n : std_logic;
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signal psram_sclk : std_logic;
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signal psram_sio : std_logic_vector(3 downto 0);
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signal flash_ce_n : std_logic;
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signal flash_sclk : std_logic;
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signal flash_sio : std_logic_vector(3 downto 0);
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signal pmod : std_logic_vector(7 downto 0);
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begin
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top_inst : entity design.top
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generic map(
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F_IN => 50000000,
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F_CLK => 25000000,
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F_CLK_PHY => 50000000,
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UART_BAUD => UART_BAUD,
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CPU => "neorv32"
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)
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port map(
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clk_in => clk_in,
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uart_tx => uart_tx,
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uart_rx => uart_rx,
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eth_rx_p => eth_rx_p,
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eth_tx_p => eth_tx_p,
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eth_tx_n => eth_tx_n,
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eth_led_green_n => eth_led_green_n,
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eth_led_orange_n => eth_led_orange_n,
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led_user => led_user,
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psram_ce_n => psram_ce_n,
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psram_sclk => psram_sclk,
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psram_sio => psram_sio,
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flash_ce_n => flash_ce_n,
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flash_sclk => flash_sclk,
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flash_sio => flash_sio,
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pmod => pmod
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);
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aps6404l_inst : entity device_models.aps6404l
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generic map(
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SIZE => 8 * 1024 * 1024,
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--MEMFILE => "../sw/demo/decrypt-1.vhex",
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LOG_EN => false
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)
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port map(
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ce_n => psram_ce_n,
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sclk => psram_sclk,
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sio => psram_sio
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);
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uart_decoder : process is
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constant DELAY : time := (1 sec / UART_BAUD);
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variable d : std_logic_vector(7 downto 0);
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variable print_time : boolean := true;
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procedure print(text : character) is
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variable lb : line;
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begin
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write(lb, text);
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write(output, lb.all);
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flush(output);
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end procedure print;
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begin
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wait until falling_edge(uart_tx);
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wait for 0.5 * DELAY;
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for i in 0 to 7 loop
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wait for DELAY;
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d(i) := uart_tx;
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end loop;
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wait for 1.0 * DELAY;
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if print_time then
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write(output, "{" & time'image(now) & "} ");
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print_time := false;
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end if;
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print(character'val(to_integer(unsigned(d))));
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if character'val(to_integer(unsigned(d))) = LF then
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print_time := true;
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end if;
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--report "UART RX: " & character'val(to_integer(unsigned(d)));
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end process uart_decoder;
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test : process is
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procedure uart_tx(d : std_logic_vector(7 downto 0)) is
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constant DELAY : time := (1 sec / UART_BAUD);
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begin
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uart_rx <= '0';
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wait for DELAY;
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for i in d'low to d'high loop
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uart_rx <= d(i);
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wait for DELAY;
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end loop;
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uart_rx <= '1';
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wait for DELAY;
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end procedure uart_tx;
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begin
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test_runner_setup(runner, runner_cfg);
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report "Waiting for internal reset to be complete...";
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wait for 10 us;
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report "Starting tests...";
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while test_suite loop
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if run("run_program") then
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uart_rx <= '1';
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wait for (1 sec / UART_BAUD) * 10;
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report ("Jumping to external RAM...");
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-- JUMP
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uart_tx(x"03");
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-- to RAM (+4, jalr zero)
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uart_tx(x"40");
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uart_tx(x"00");
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uart_tx(x"00");
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uart_tx(x"00");
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report ("This is a manual test. Add wait statement here and watch the output...");
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wait for 0 ns;
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report ("Stopping test.");
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end if;
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end loop;
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test_runner_cleanup(runner);
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end process test;
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test_runner_watchdog(runner, 1000 ms);
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk_in <= '0';
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wait for period / 2;
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clk_in <= '1';
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wait for period - (period / 2);
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end process clock_driver;
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end architecture RTL;
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@ -237,10 +237,10 @@ begin
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servant_rom_vhdl_inst : entity work.servant_ram_vhdl
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servant_rom_vhdl_inst : entity work.servant_ram_vhdl
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generic map(
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generic map(
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memfile => "../sw/bootrom/bootrom.vhex",
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memfile => "../sw/bootrom/bootrom.vhex",
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read_only => true,
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read_only => true,
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adr_width => 9,
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adr_width => 9,
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force_vlog => not in_simulation -- GHDL + Yosys doesn't keep the memfile
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force_vlog => not in_simulation -- GHDL + Yosys doesn't keep the memfile
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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@ -16,7 +16,9 @@ use std.textio.all;
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entity aps6404l is
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entity aps6404l is
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generic(
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generic(
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LOG_EN : boolean := true
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SIZE : natural := 1024;
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LOG_EN : boolean := true;
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MEMFILE : string := ""
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);
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);
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port(
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port(
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ce_n : in std_logic;
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ce_n : in std_logic;
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@ -41,7 +43,24 @@ begin
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test : process is
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test : process is
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type rx_state_t is (COMMAND, READ, WRITE, COMPLETE);
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type rx_state_t is (COMMAND, READ, WRITE, COMPLETE);
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type byte_vector is array (natural range <>) of std_logic_vector(7 downto 0);
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type byte_vector is array (natural range <>) of std_logic_vector(7 downto 0);
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variable mem : byte_vector(0 to 1023);
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subtype mem_t is byte_vector(0 to SIZE - 1);
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impure function init_ram_hex return mem_t is
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file text_file : text;
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variable text_line : line;
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variable ram_content : mem_t := (others => x"5A");
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begin
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if MEMFILE /= "" then
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file_open(text_file, MEMFILE, read_mode);
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for i in 0 to SIZE - 1 loop
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exit when endfile(text_file);
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readline(text_file, text_line);
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hread(text_line, ram_content(i));
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end loop;
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end if;
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return ram_content;
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end function;
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variable mem : mem_t := init_ram_hex;
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variable bytes : byte_vector(0 to 32);
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variable bytes : byte_vector(0 to 32);
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variable cnt, bytecnt : integer;
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variable cnt, bytecnt : integer;
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variable state : rx_state_t;
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variable state : rx_state_t;
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@ -111,8 +130,13 @@ begin
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print(" Addr: " & to_hstring(bytes(1)) & to_hstring(bytes(2)) & to_hstring(bytes(3)));
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print(" Addr: " & to_hstring(bytes(1)) & to_hstring(bytes(2)) & to_hstring(bytes(3)));
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addr := to_integer(unsigned(std_logic_vector'(bytes(1), bytes(2), bytes(3))));
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addr := to_integer(unsigned(std_logic_vector'(bytes(1), bytes(2), bytes(3))));
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elsif bytecnt > 4 then
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elsif bytecnt > 4 then
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dout := mem(addr);
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if addr < SIZE then
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print(" Read " & integer'image(addr) & ": " & to_hstring(mem(addr)));
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dout := mem(addr);
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print(" Read " & integer'image(addr) & ": " & to_hstring(mem(addr)));
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else
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dout := (others => 'X');
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print(" Read " & integer'image(addr) & ": OUT-OF-BOUNDS");
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end if;
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addr := addr + 1;
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addr := addr + 1;
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end if;
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end if;
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@ -122,8 +146,12 @@ begin
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addr := to_integer(unsigned(std_logic_vector'(bytes(1), bytes(2), bytes(3))));
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addr := to_integer(unsigned(std_logic_vector'(bytes(1), bytes(2), bytes(3))));
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elsif bytecnt > 3 then
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elsif bytecnt > 3 then
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print(" Write " & integer'image(addr) & ": " & to_hstring(bytes(bytecnt)));
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print(" Write " & integer'image(addr) & ": " & to_hstring(bytes(bytecnt)));
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mem(addr) := bytes(bytecnt);
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if (addr < SIZE) then
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addr := addr + 1;
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mem(addr) := bytes(bytecnt);
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else
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print(" Error: OUT OF BOUNDS access! Ignoring write.");
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end if;
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addr := addr + 1;
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end if;
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end if;
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when COMPLETE =>
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when COMPLETE =>
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14
fpga/patch_asserts.sh
Executable file
14
fpga/patch_asserts.sh
Executable file
@ -0,0 +1,14 @@
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#!/bin/bash
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file="$1"
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echo "Removing \$assert from $file..."
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LOCS=`grep -n '$assert' "$file" | sed 's/:.*//g'`
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IFS=$'\n'
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for LOC in $LOCS; do
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START=$(($LOC-2))
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END=$(($LOC+14))
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echo "Deleting lines $START -> $END"
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sed -i -e "${START},${END}d" "$file"
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done
|
@ -57,6 +57,7 @@ if not "osvvm" in libs:
|
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vu.add_compile_option("ghdl.a_flags", ["-frelaxed", "-fsynopsys"])
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vu.add_compile_option("ghdl.a_flags", ["-frelaxed", "-fsynopsys"])
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vu.add_compile_option("nvc.a_flags", ["--relaxed"])
|
vu.add_compile_option("nvc.a_flags", ["--relaxed"])
|
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#vu.set_sim_option("nvc.elab_flags", ["-O3"])
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#vu.set_sim_option("nvc.elab_flags", ["-O3"])
|
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vu.set_sim_option("nvc.sim_flags", ["--format=fst", "--wave=wave.fst"])
|
vu.set_sim_option("nvc.heap_size", "256M")
|
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|
vu.set_sim_option("nvc.sim_flags", ["--format=fst", "--wave=wave.fst", "--dump-arrays"])
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|
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vu.main()
|
vu.main()
|
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|
Loading…
Reference in New Issue
Block a user