|
|
01df956317
|
Fix a variety of bugs found during integration
|
2019-06-22 17:24:09 +02:00 |
|
|
|
28adf2340b
|
Add FDEF for single-cell FPGA
|
2019-06-21 21:17:32 +02:00 |
|
|
|
ae2e6552ce
|
Add option to generate binary or ASCII hex bitstreams
|
2019-06-21 21:16:46 +02:00 |
|
|
|
7df813fc71
|
Add argument parsing
|
2019-06-21 20:57:56 +02:00 |
|
|
|
0834cf0c0d
|
Finish basic bitstream generator
|
2019-06-21 20:31:34 +02:00 |
|
|
|
5d86f8c7cf
|
Start bitstream generator
|
2019-06-20 13:45:04 +02:00 |
|
|
|
a1d635889c
|
Clean up
|
2019-06-19 18:32:59 +02:00 |
|
|
|
925e17372a
|
Implement fpga_isp_chain_new
|
2019-06-19 18:25:21 +02:00 |
|
|
|
d0fed3cce4
|
Implement ISP chain walker
|
2019-06-18 20:15:35 +02:00 |
|
|
|
cf80ff7b6b
|
Reverse order of log levels
|
2019-06-17 22:08:24 +02:00 |
|
|
|
0309934d82
|
Add comments for later cleanups
|
2019-06-17 22:08:11 +02:00 |
|
|
|
e12120fade
|
Start implementing Kousaten
|
2019-06-16 21:27:42 +02:00 |
|
|
|
0072ed418b
|
Initialize CMakeProject for Kousaten
|
2019-06-16 17:11:20 +02:00 |
|
|
|
7544e4256a
|
Configure Gerber export for PCBWay
|
2019-06-16 13:40:37 +02:00 |
|
|
|
b8c465da70
|
Add power LED label
|
2019-06-16 13:20:47 +02:00 |
|
|
|
2de7b3ec6c
|
Add part numbers to silkscreen
|
2019-06-16 13:18:15 +02:00 |
|
|
|
1f72590231
|
Make some minor adjustments
|
2019-06-15 12:57:17 +02:00 |
|
|
|
685bc88045
|
Change Schottky footprint to SOD123
|
2019-06-15 11:47:19 +02:00 |
|
|
|
58ad3a75c5
|
Cover the board in silkscreen
|
2019-06-14 20:42:09 +02:00 |
|
|
|
718d70132b
|
Add MokM0d logo
|
2019-06-14 19:51:25 +02:00 |
|
|
|
45827f239a
|
Clean up silkscreen
|
2019-06-13 19:47:35 +02:00 |
|
|
|
9f96e5cf82
|
Editiorial
|
2019-06-13 19:19:26 +02:00 |
|
|
|
01043be425
|
Remove incorrect junction
Fixes #7.
|
2019-06-13 19:18:58 +02:00 |
|
|
|
dc5b791b6d
|
Finish layout
|
2019-06-13 19:16:26 +02:00 |
|
|
|
339fb214d7
|
Continue work on rev 1
|
2019-06-11 21:50:54 +02:00 |
|
|
|
1c6ae29a8f
|
Layout rev 1
|
2019-06-10 19:48:44 +02:00 |
|
|
|
f85577c0f1
|
Reset routing, place all components
|
2019-06-10 17:27:15 +02:00 |
|
|
|
a1046d75b8
|
Continue trial layout
|
2019-06-10 14:25:54 +02:00 |
|
|
|
fc94685478
|
Every day I'm layoutin'
|
2019-06-09 23:22:42 +02:00 |
|
|
|
a9d8d0e654
|
doc: Add notes
|
2019-06-06 21:25:18 +02:00 |
|
|
|
01918678ce
|
Add licensing information
|
2019-06-06 20:45:55 +02:00 |
|
|
|
8b80a78b3b
|
Layout input muxing
|
2019-06-05 23:32:39 +02:00 |
|
|
|
b15d865090
|
Start layout
|
2019-06-04 22:43:08 +02:00 |
|
|
|
a2608f41ae
|
Ignore BOM
|
2019-06-04 22:42:56 +02:00 |
|
|
|
5bcc79e505
|
Create copy of kicad design to optimize for layout
|
2019-06-04 21:15:25 +02:00 |
|
|
|
2c21b9191c
|
Move kicad design into separate directory
|
2019-06-04 21:14:25 +02:00 |
|
|
|
798144c729
|
Update global project config for PCBWay's rules
|
2019-06-04 21:11:08 +02:00 |
|
|
|
a62036545c
|
Reannotate schematic
|
2019-06-04 21:05:23 +02:00 |
|
|
|
5ecdc8c13d
|
Clean up
|
2019-06-04 20:57:14 +02:00 |
|
|
|
7b7d467935
|
Add power LED and bulk capacitor
|
2019-06-04 20:51:59 +02:00 |
|
|
|
9eaef0c055
|
Swap L and T bus on input MUX
|
2019-06-01 22:42:13 +02:00 |
|
|
|
104cc9c9c9
|
Flip top and bottom connectors
That way, pin 1 is always left or top.
|
2019-06-01 22:22:40 +02:00 |
|
|
|
626dbde9fe
|
Change input LUT mapping to allow F3 access in mode-3
|
2019-06-01 22:03:01 +02:00 |
|
|
|
f762348d03
|
Fix footprint of U14
|
2019-06-01 18:33:12 +02:00 |
|
|
|
2c162e729b
|
Fix DRC issues
Fixes #6.
|
2019-06-01 18:31:45 +02:00 |
|
|
|
6b2fa97a6f
|
Fix right and bottom bus connections
Fixes #2.
|
2019-06-01 18:20:26 +02:00 |
|
|
|
76b1d2d01f
|
Annotate, and assign preliminary parts
|
2019-06-01 18:12:15 +02:00 |
|
|
|
037d13c5f6
|
Exchange fabric2 with fabric3 on input MUX 2
Resolves #1.
|
2019-06-01 17:51:20 +02:00 |
|
|
|
28b9ad42c3
|
Change gender of right and bottom connector
|
2019-05-31 22:19:01 +02:00 |
|
|
|
5445fa2831
|
Editorial
|
2019-05-31 22:14:42 +02:00 |
|
