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9b3da0fd87
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Fix LUT3/4 selection logic
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2019-05-31 20:36:29 +02:00 |
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37c33e8200
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Include LUTD config in bit map
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2019-05-31 20:36:00 +02:00 |
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e66cd09c68
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Add LEDs
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2019-05-31 18:52:59 +02:00 |
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6cbafd76a3
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Implement PCB top level
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2019-05-31 18:06:53 +02:00 |
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d630a3ee84
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Redesign routing and input muxing
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2019-05-31 16:36:08 +02:00 |
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1f3df7f87c
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Add bypass caps and clean up a bit
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2019-05-30 21:36:22 +02:00 |
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bf55a828a8
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Fix LUT split enable logic
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2019-05-30 21:12:52 +02:00 |
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9be0ea5ed4
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Design first draft of core logic
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2019-05-30 20:24:33 +02:00 |
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