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72dabd64db
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sw: Swap the order of the two LUTs in the bitstream
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2019-09-23 21:25:27 +02:00 |
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f27c728472
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sw: Implement bodgefix for schematic rev 03L
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2019-09-22 19:11:43 +02:00 |
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30c83a658f
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sw: Fix fpga_cell_lut34_lut_get_out_mux
Was accessing wrong data when generating info for set 2.
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2019-09-22 19:11:21 +02:00 |
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0a493bdd2a
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Remove unnecessary debug output
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2019-09-13 13:02:05 +09:00 |
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a072dbfe8a
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Fix unnecessary semicolon warnings in bit set / unset macros
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2019-09-13 12:59:24 +09:00 |
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a2abccfc5d
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Fix output MUX selection logic
Fixes #15.
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2019-09-13 12:55:32 +09:00 |
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7abcead6a9
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des: Fix data type of drive_sel
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2019-09-13 12:48:28 +09:00 |
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f60d76f831
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Fix sync polarity
Fixes #11.
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2019-06-29 12:48:26 +02:00 |
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9a06c054e8
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Fix bitstream generator collision check
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2019-06-29 12:37:59 +02:00 |
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29efb7446b
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Add spreadsheet to help generate LUT configs
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2019-06-22 17:50:42 +02:00 |
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0de1c093cd
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Add program.sh script
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2019-06-22 17:47:20 +02:00 |
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15fe4e4ca3
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Add test configuration for 2-bit counter
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2019-06-22 17:24:44 +02:00 |
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6846aff71d
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Add debug print for bitstream bits
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2019-06-22 17:24:26 +02:00 |
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01df956317
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Fix a variety of bugs found during integration
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2019-06-22 17:24:09 +02:00 |
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28adf2340b
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Add FDEF for single-cell FPGA
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2019-06-21 21:17:32 +02:00 |
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ae2e6552ce
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Add option to generate binary or ASCII hex bitstreams
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2019-06-21 21:16:46 +02:00 |
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7df813fc71
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Add argument parsing
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2019-06-21 20:57:56 +02:00 |
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0834cf0c0d
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Finish basic bitstream generator
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2019-06-21 20:31:34 +02:00 |
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5d86f8c7cf
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Start bitstream generator
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2019-06-20 13:45:04 +02:00 |
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a1d635889c
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Clean up
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2019-06-19 18:32:59 +02:00 |
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925e17372a
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Implement fpga_isp_chain_new
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2019-06-19 18:25:21 +02:00 |
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d0fed3cce4
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Implement ISP chain walker
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2019-06-18 20:15:35 +02:00 |
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cf80ff7b6b
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Reverse order of log levels
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2019-06-17 22:08:24 +02:00 |
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0309934d82
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Add comments for later cleanups
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2019-06-17 22:08:11 +02:00 |
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e12120fade
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Start implementing Kousaten
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2019-06-16 21:27:42 +02:00 |
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0072ed418b
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Initialize CMakeProject for Kousaten
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2019-06-16 17:11:20 +02:00 |
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7544e4256a
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Configure Gerber export for PCBWay
|
2019-06-16 13:40:37 +02:00 |
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b8c465da70
|
Add power LED label
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2019-06-16 13:20:47 +02:00 |
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2de7b3ec6c
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Add part numbers to silkscreen
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2019-06-16 13:18:15 +02:00 |
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1f72590231
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Make some minor adjustments
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2019-06-15 12:57:17 +02:00 |
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685bc88045
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Change Schottky footprint to SOD123
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2019-06-15 11:47:19 +02:00 |
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58ad3a75c5
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Cover the board in silkscreen
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2019-06-14 20:42:09 +02:00 |
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718d70132b
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Add MokM0d logo
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2019-06-14 19:51:25 +02:00 |
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45827f239a
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Clean up silkscreen
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2019-06-13 19:47:35 +02:00 |
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9f96e5cf82
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Editiorial
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2019-06-13 19:19:26 +02:00 |
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01043be425
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Remove incorrect junction
Fixes #7.
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2019-06-13 19:18:58 +02:00 |
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dc5b791b6d
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Finish layout
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2019-06-13 19:16:26 +02:00 |
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339fb214d7
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Continue work on rev 1
|
2019-06-11 21:50:54 +02:00 |
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1c6ae29a8f
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Layout rev 1
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2019-06-10 19:48:44 +02:00 |
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f85577c0f1
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Reset routing, place all components
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2019-06-10 17:27:15 +02:00 |
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a1046d75b8
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Continue trial layout
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2019-06-10 14:25:54 +02:00 |
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fc94685478
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Every day I'm layoutin'
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2019-06-09 23:22:42 +02:00 |
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a9d8d0e654
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doc: Add notes
|
2019-06-06 21:25:18 +02:00 |
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01918678ce
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Add licensing information
|
2019-06-06 20:45:55 +02:00 |
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8b80a78b3b
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Layout input muxing
|
2019-06-05 23:32:39 +02:00 |
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b15d865090
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Start layout
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2019-06-04 22:43:08 +02:00 |
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a2608f41ae
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Ignore BOM
|
2019-06-04 22:42:56 +02:00 |
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5bcc79e505
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Create copy of kicad design to optimize for layout
|
2019-06-04 21:15:25 +02:00 |
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2c21b9191c
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Move kicad design into separate directory
|
2019-06-04 21:14:25 +02:00 |
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798144c729
|
Update global project config for PCBWay's rules
|
2019-06-04 21:11:08 +02:00 |
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