Markus Koch markus
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markus pushed to test at fpga/trashernet 2021-09-25 20:36:45 +02:00
18b4213ed0 doc: Add Trashernet logo
10da238c60 mac: Refactor to use records for the application interface
cfac94136a phy: Refactor to use records for the application interface
cf6fb61195 mac: Use records for header fields
9addd97b57 Rename types package to general trashernet package
markus pushed to master at fpga/trashernet 2021-09-25 20:30:22 +02:00
18b4213ed0 doc: Add Trashernet logo
markus pushed to master at fpga/trashernet 2021-09-25 16:19:43 +02:00
10da238c60 mac: Refactor to use records for the application interface
markus pushed to master at fpga/trashernet 2021-09-25 12:29:50 +02:00
cfac94136a phy: Refactor to use records for the application interface
markus pushed to master at fpga/trashernet 2021-09-25 12:21:35 +02:00
cf6fb61195 mac: Use records for header fields
1d9560fb08 mac: Use records for header fields
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markus pushed to master at fpga/trashernet 2021-09-25 11:22:54 +02:00
1d9560fb08 mac: Use records for header fields
0ebd9290f2 mac: Use records for header fields
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markus pushed to master at fpga/trashernet 2021-09-25 11:22:05 +02:00
0ebd9290f2 mac: Use records for header fields
markus pushed to master at fpga/trashernet 2021-09-25 11:08:58 +02:00
9addd97b57 Rename types package to general trashernet package
markus pushed to master at fpga/trashernet 2021-09-04 19:35:09 +02:00
1bff61d24a Fix code formatting
743d2465d9 Add license headers
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markus pushed to master at fpga/trashernet 2021-09-04 19:17:21 +02:00
35093bba85 bench: Test MAC TX
2bee387081 mac: Implement TX path
5a1363615f bench: Update PHY ports
29bbb50f6a phy: tx: Fix TX startup handling
9afdb984f9 phy: tx: Pass tx_n through the CDC wrapper
Compare 7 commits »
markus opened issue fpga/trashernet#2 2021-09-04 19:13:43 +02:00
Don't process Manchester timing right from the start
markus pushed to master at fpga/trashernet 2021-08-31 20:37:58 +02:00
16026849e8 phy: tx: Implement transmitter
263b03e5db phy: tx: Implement transmitter
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markus pushed to master at fpga/trashernet 2021-08-31 20:36:48 +02:00
263b03e5db phy: tx: Implement transmitter
6322f5a317 Add trashernet_types package
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markus opened issue fpga/trashernet#1 2021-08-30 13:33:49 +02:00
Calculate CRC from serial bitstream
markus pushed to master at fpga/trashernet 2021-08-30 13:28:53 +02:00
3775dc336b mac: Add MAC RX
76301f0a97 bench: Add IPG after send_data
1f353fcb2f phy: rx: Do not reset rx_data to save resources
355bbc5ab1 mac: Add generic CRC
775024e91f bench: Add basic test bench for PHY
Compare 5 commits »
markus pushed to master at fpga/trashernet 2021-08-28 19:10:35 +02:00
dddfdbabc1 phy: Add CDC wrapper
d16f1afd9a phy: Rename rx/tx signals
3900d454f9 misc: Allow dynamic length for synchronizer
Compare 3 commits »
markus pushed to master at fpga/trashernet 2021-08-28 14:27:23 +02:00
38f96cdc63 phy: rx: Come up in disconnected state after reset
0133fa8cce phy: rx: Fix bit order
9e5b958f46 phy: rx: Reset transition analyzer state at the EOT
f5f643287f phy: rx: Cleanup
1f894866ab phy: rx: Implement error handling for Manchester
Compare 6 commits »
markus pushed to master at fpga/trashernet 2021-08-27 20:15:40 +02:00
08bd5f166b Implement PHY RX
b0b15fa767 Implement PHY RX
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markus deleted tag master from fpga/trashernet 2021-08-27 20:13:14 +02:00
markus pushed to master at fpga/trashernet 2021-08-27 20:13:14 +02:00
b0b15fa767 Implement PHY RX
85f3a3021a Initial commit