Markus Perkins markus
markus pushed to feature/mii at fpga/trashernet 2025-10-10 15:51:53 +02:00
d9d05c8123 Add MII PHY
7cb86523ba rmii: Reset some more signals
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markus created branch feature/mii in fpga/trashernet 2025-10-10 15:51:52 +02:00
markus pushed to master at fpga/trashernet 2025-10-07 13:43:58 +02:00
3a42c865c6 udpprot: Add round-robin scheduler
markus commented on issue fpga/trashernet#15 2025-09-30 16:05:09 +02:00
Implement UDP Layer

Implemented as trashernet_udp and trashernet_udpprot.

markus closed issue fpga/trashernet#15 2025-09-30 16:05:09 +02:00
Implement UDP Layer
markus pushed to master at fpga/trashernet 2025-09-30 16:04:08 +02:00
474d444f59 udpprot: Fix end-of-packet detection in mux
a98a9cbf06 udpprot: Prioritize rx/tx mux sources the same way
6e616c5f35 ipv4: Only forward rx_ok/error strobes when addressed
f13e9bf907 ipv4: Fix header parsing
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markus pushed to master at fpga/trashernet 2025-09-23 15:45:37 +02:00
ac553483df rmii: Fix CDC for *_active
markus pushed to master at fpga/trashernet 2025-09-23 13:21:17 +02:00
faa915824a rmii: Do not prepend sync header
markus pushed to master at fpga/trashernet 2025-09-19 10:10:04 +02:00
3c592dbd23 doc: Document UDP modules
markus pushed to master at fpga/trashernet 2025-09-19 10:09:08 +02:00
ba0cbed9bf bench: hw_itl: Use UDPprot
e7db2df389 udp: Fix length field
3e1a53abaf Move header fields into records
c9f6560091 Add RMII PHY
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markus pushed to feature/rmii at fpga/trashernet 2025-09-19 10:08:49 +02:00
markus pushed to feature/rmii at fpga/trashernet 2025-09-19 10:08:06 +02:00
d2a8e70ecc design: hw_itl: Change gateway to an address different from the testing system
markus pushed to feature/rmii at fpga/trashernet 2025-09-19 09:59:45 +02:00
ba0cbed9bf bench: hw_itl: Use UDPprot
e7db2df389 udp: Fix length field
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markus pushed to feature/rmii at fpga/trashernet 2025-09-11 12:46:21 +02:00
3e1a53abaf Move header fields into records
markus pushed to feature/rmii at fpga/trashernet 2025-09-11 10:40:40 +02:00
c9f6560091 Add RMII PHY
markus pushed to feature/rmii at fpga/trashernet 2025-09-11 10:24:42 +02:00
276eece852 Add RMII PHY
markus created branch feature/rmii in fpga/trashernet 2025-09-11 10:21:39 +02:00
markus pushed to feature/rmii at fpga/trashernet 2025-09-11 10:21:39 +02:00
fe3813ca24 Add RMII PHY
markus opened issue fpga/trashernet#22 2025-09-11 08:56:10 +02:00
PHY CDC tx_data_en pulses might get filtered
markus closed issue fpga/trashernet#13 2025-09-02 14:01:52 +02:00
⚠️ ETH and IPv4prot muxing fails when two access in the same cycle