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Markus Koch
markus
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1 Following
Germany
https://notsyncing.net
Joined on
2016-05-11
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15
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Starred Repositories
markus
pushed to
master
at
fpga/trashernet
2021-09-04 19:17:21 +02:00
35093bba85
bench: Test MAC TX
2bee387081
mac: Implement TX path
5a1363615f
bench: Update PHY ports
29bbb50f6a
phy: tx: Fix TX startup handling
9afdb984f9
phy: tx: Pass tx_n through the CDC wrapper
Compare 7 commits »
markus
opened issue
fpga/trashernet#2
2021-09-04 19:13:43 +02:00
Don't process Manchester timing right from the start
markus
pushed to
master
at
fpga/trashernet
2021-08-31 20:37:58 +02:00
16026849e8
phy: tx: Implement transmitter
263b03e5db
phy: tx: Implement transmitter
Compare 2 commits »
markus
pushed to
master
at
fpga/trashernet
2021-08-31 20:36:48 +02:00
263b03e5db
phy: tx: Implement transmitter
6322f5a317
Add trashernet_types package
Compare 2 commits »
markus
opened issue
fpga/trashernet#1
2021-08-30 13:33:49 +02:00
Calculate CRC from serial bitstream
markus
pushed to
master
at
fpga/trashernet
2021-08-30 13:28:53 +02:00
3775dc336b
mac: Add MAC RX
76301f0a97
bench: Add IPG after send_data
1f353fcb2f
phy: rx: Do not reset rx_data to save resources
355bbc5ab1
mac: Add generic CRC
775024e91f
bench: Add basic test bench for PHY
Compare 5 commits »
markus
pushed to
master
at
fpga/trashernet
2021-08-28 19:10:35 +02:00
dddfdbabc1
phy: Add CDC wrapper
d16f1afd9a
phy: Rename rx/tx signals
3900d454f9
misc: Allow dynamic length for synchronizer
Compare 3 commits »
markus
pushed to
master
at
fpga/trashernet
2021-08-28 14:27:23 +02:00
38f96cdc63
phy: rx: Come up in disconnected state after reset
0133fa8cce
phy: rx: Fix bit order
9e5b958f46
phy: rx: Reset transition analyzer state at the EOT
f5f643287f
phy: rx: Cleanup
1f894866ab
phy: rx: Implement error handling for Manchester
Compare 6 commits »
markus
pushed to
master
at
fpga/trashernet
2021-08-27 20:15:40 +02:00
08bd5f166b
Implement PHY RX
b0b15fa767
Implement PHY RX
Compare 2 commits »
markus
deleted tag master from
fpga/trashernet
2021-08-27 20:13:14 +02:00
markus
pushed to
master
at
fpga/trashernet
2021-08-27 20:13:14 +02:00
b0b15fa767
Implement PHY RX
85f3a3021a
Initial commit
markus
created repository
fpga/trashernet
2021-08-27 20:13:02 +02:00
markus
deleted tag master from
scripts/eth_over_uart
2021-08-21 21:54:08 +02:00
markus
pushed to
master
at
scripts/eth_over_uart
2021-08-21 21:54:08 +02:00
6981889ea0
Initial commit
markus
created repository
scripts/eth_over_uart
2021-08-21 21:53:56 +02:00
markus
pushed to
master
at
electronics/sabik-cpu
2021-07-17 23:08:17 +02:00
632772d4b7
Document WS2812B level shifter erratum
markus
pushed to
wip_rgbed
at
electronics/sabik-cpu
2021-07-17 23:05:49 +02:00
d5ac0d7277
wip: Adapt for RGBed
618124ab83
wip: Adapt for RGBed
Compare 2 commits »
markus
deleted tag wip_rgbed from
electronics/sabik-cpu
2021-07-17 17:33:47 +02:00
markus
pushed to
wip_rgbed
at
electronics/sabik-cpu
2021-07-17 17:33:47 +02:00
618124ab83
wip: Adapt for RGBed
08a2581297
Use git describe for the REVISION define
18f405aa46
Configure LEDs
59dcbaf177
Remove debug printfs
154980ee10
Print git revision on startup
markus
opened issue
markus/lifo-dijkstraserv#9
2021-07-01 20:20:33 +02:00
Route 430,66 to -375,3954 fails to use station
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