Compare commits

...

66 Commits
rev01 ... sw

Author SHA1 Message Date
Markus Koch 30e18b4357 sw: Add 16-bit counter demo 2019-09-27 15:23:03 +02:00
Markus Koch 6fbdcf9016 sw: Fix coding style 2019-09-23 21:29:36 +02:00
Markus Koch 7bb7049eea sw: Fix logic to determine when to enable the output drivers
Before, it was always enabling all outputs,
even when they should have been tristated.
2019-09-23 21:28:54 +02:00
Markus Koch 98a7a5d170 sw: Create function to determine whether an output is driven 2019-09-23 21:27:45 +02:00
Markus Koch 953818f43c sw: Report if bit is unset in final bitstream result 2019-09-23 21:26:50 +02:00
Markus Koch 72dabd64db sw: Swap the order of the two LUTs in the bitstream 2019-09-23 21:25:27 +02:00
Markus Koch f27c728472 sw: Implement bodgefix for schematic rev 03L 2019-09-22 19:11:43 +02:00
Markus Koch 30c83a658f sw: Fix fpga_cell_lut34_lut_get_out_mux
Was accessing wrong data when generating info for set 2.
2019-09-22 19:11:21 +02:00
Markus Koch 0a493bdd2a Remove unnecessary debug output 2019-09-13 13:02:05 +09:00
Markus Koch a072dbfe8a Fix unnecessary semicolon warnings in bit set / unset macros 2019-09-13 12:59:24 +09:00
Markus Koch a2abccfc5d Fix output MUX selection logic
Fixes #15.
2019-09-13 12:55:32 +09:00
Markus Koch 7abcead6a9 des: Fix data type of drive_sel 2019-09-13 12:48:28 +09:00
Markus Koch f60d76f831 Fix sync polarity
Fixes #11.
2019-06-29 12:48:26 +02:00
Markus Koch 9a06c054e8 Fix bitstream generator collision check 2019-06-29 12:37:59 +02:00
Markus Koch 29efb7446b Add spreadsheet to help generate LUT configs 2019-06-22 17:50:42 +02:00
Markus Koch 0de1c093cd Add program.sh script 2019-06-22 17:47:20 +02:00
Markus Koch 15fe4e4ca3 Add test configuration for 2-bit counter 2019-06-22 17:24:44 +02:00
Markus Koch 6846aff71d Add debug print for bitstream bits 2019-06-22 17:24:26 +02:00
Markus Koch 01df956317 Fix a variety of bugs found during integration 2019-06-22 17:24:09 +02:00
Markus Koch 28adf2340b Add FDEF for single-cell FPGA 2019-06-21 21:17:32 +02:00
Markus Koch ae2e6552ce Add option to generate binary or ASCII hex bitstreams 2019-06-21 21:16:46 +02:00
Markus Koch 7df813fc71 Add argument parsing 2019-06-21 20:57:56 +02:00
Markus Koch 0834cf0c0d Finish basic bitstream generator 2019-06-21 20:31:34 +02:00
Markus Koch 5d86f8c7cf Start bitstream generator 2019-06-20 13:45:04 +02:00
Markus Koch a1d635889c Clean up 2019-06-19 18:32:59 +02:00
Markus Koch 925e17372a Implement fpga_isp_chain_new 2019-06-19 18:25:21 +02:00
Markus Koch d0fed3cce4 Implement ISP chain walker 2019-06-18 20:15:35 +02:00
Markus Koch cf80ff7b6b Reverse order of log levels 2019-06-17 22:08:24 +02:00
Markus Koch 0309934d82 Add comments for later cleanups 2019-06-17 22:08:11 +02:00
Markus Koch e12120fade Start implementing Kousaten 2019-06-16 21:27:42 +02:00
Markus Koch 0072ed418b Initialize CMakeProject for Kousaten 2019-06-16 17:11:20 +02:00
Markus Koch 7544e4256a Configure Gerber export for PCBWay 2019-06-16 13:40:37 +02:00
Markus Koch b8c465da70 Add power LED label 2019-06-16 13:20:47 +02:00
Markus Koch 2de7b3ec6c Add part numbers to silkscreen 2019-06-16 13:18:15 +02:00
Markus Koch 1f72590231 Make some minor adjustments 2019-06-15 12:57:17 +02:00
Markus Koch 685bc88045 Change Schottky footprint to SOD123 2019-06-15 11:47:19 +02:00
Markus Koch 58ad3a75c5 Cover the board in silkscreen 2019-06-14 20:42:09 +02:00
Markus Koch 718d70132b Add MokM0d logo 2019-06-14 19:51:25 +02:00
Markus Koch 45827f239a Clean up silkscreen 2019-06-13 19:47:35 +02:00
Markus Koch 9f96e5cf82 Editiorial 2019-06-13 19:19:26 +02:00
Markus Koch 01043be425 Remove incorrect junction
Fixes #7.
2019-06-13 19:18:58 +02:00
Markus Koch dc5b791b6d Finish layout 2019-06-13 19:16:26 +02:00
Markus Koch 339fb214d7 Continue work on rev 1 2019-06-11 21:50:54 +02:00
Markus Koch 1c6ae29a8f Layout rev 1 2019-06-10 19:48:44 +02:00
Markus Koch f85577c0f1 Reset routing, place all components 2019-06-10 17:27:15 +02:00
Markus Koch a1046d75b8 Continue trial layout 2019-06-10 14:25:54 +02:00
Markus Koch fc94685478 Every day I'm layoutin' 2019-06-09 23:22:42 +02:00
Markus Koch a9d8d0e654 doc: Add notes 2019-06-06 21:25:18 +02:00
Markus Koch 01918678ce Add licensing information 2019-06-06 20:45:55 +02:00
Markus Koch 8b80a78b3b Layout input muxing 2019-06-05 23:32:39 +02:00
Markus Koch b15d865090 Start layout 2019-06-04 22:43:08 +02:00
Markus Koch a2608f41ae Ignore BOM 2019-06-04 22:42:56 +02:00
Markus Koch 5bcc79e505 Create copy of kicad design to optimize for layout 2019-06-04 21:15:25 +02:00
Markus Koch 2c21b9191c Move kicad design into separate directory 2019-06-04 21:14:25 +02:00
Markus Koch 798144c729 Update global project config for PCBWay's rules 2019-06-04 21:11:08 +02:00
Markus Koch a62036545c Reannotate schematic 2019-06-04 21:05:23 +02:00
Markus Koch 5ecdc8c13d Clean up 2019-06-04 20:57:14 +02:00
Markus Koch 7b7d467935 Add power LED and bulk capacitor 2019-06-04 20:51:59 +02:00
Markus Koch 9eaef0c055 Swap L and T bus on input MUX 2019-06-01 22:42:13 +02:00
Markus Koch 104cc9c9c9 Flip top and bottom connectors
That way, pin 1 is always left or top.
2019-06-01 22:22:40 +02:00
Markus Koch 626dbde9fe Change input LUT mapping to allow F3 access in mode-3 2019-06-01 22:03:01 +02:00
Markus Koch f762348d03 Fix footprint of U14 2019-06-01 18:33:12 +02:00
Markus Koch 2c162e729b Fix DRC issues
Fixes #6.
2019-06-01 18:31:45 +02:00
Markus Koch 6b2fa97a6f Fix right and bottom bus connections
Fixes #2.
2019-06-01 18:20:26 +02:00
Markus Koch 76b1d2d01f Annotate, and assign preliminary parts 2019-06-01 18:12:15 +02:00
Markus Koch 037d13c5f6 Exchange fabric2 with fabric3 on input MUX 2
Resolves #1.
2019-06-01 17:51:20 +02:00
45 changed files with 18168 additions and 809 deletions

1
.gitignore vendored
View File

@ -5,3 +5,4 @@
fp-info-cache
*.pdf
*.plt
*bom*

428
LICENSE.txt Normal file
View File

@ -0,0 +1,428 @@
Attribution-ShareAlike 4.0 International
=======================================================================
Creative Commons Corporation ("Creative Commons") is not a law firm and
does not provide legal services or legal advice. Distribution of
Creative Commons public licenses does not create a lawyer-client or
other relationship. Creative Commons makes its licenses and related
information available on an "as-is" basis. Creative Commons gives no
warranties regarding its licenses, any material licensed under their
terms and conditions, or any related information. Creative Commons
disclaims all liability for damages resulting from their use to the
fullest extent possible.
Using Creative Commons Public Licenses
Creative Commons public licenses provide a standard set of terms and
conditions that creators and other rights holders may use to share
original works of authorship and other material subject to copyright
and certain other rights specified in the public license below. The
following considerations are for informational purposes only, are not
exhaustive, and do not form part of our licenses.
Considerations for licensors: Our public licenses are
intended for use by those authorized to give the public
permission to use material in ways otherwise restricted by
copyright and certain other rights. Our licenses are
irrevocable. Licensors should read and understand the terms
and conditions of the license they choose before applying it.
Licensors should also secure all rights necessary before
applying our licenses so that the public can reuse the
material as expected. Licensors should clearly mark any
material not subject to the license. This includes other CC-
licensed material, or material used under an exception or
limitation to copyright. More considerations for licensors:
wiki.creativecommons.org/Considerations_for_licensors
Considerations for the public: By using one of our public
licenses, a licensor grants the public permission to use the
licensed material under specified terms and conditions. If
the licensor's permission is not necessary for any reason--for
example, because of any applicable exception or limitation to
copyright--then that use is not regulated by the license. Our
licenses grant only permissions under copyright and certain
other rights that a licensor has authority to grant. Use of
the licensed material may still be restricted for other
reasons, including because others have copyright or other
rights in the material. A licensor may make special requests,
such as asking that all changes be marked or described.
Although not required by our licenses, you are encouraged to
respect those requests where reasonable. More considerations
for the public:
wiki.creativecommons.org/Considerations_for_licensees
=======================================================================
Creative Commons Attribution-ShareAlike 4.0 International Public
License
By exercising the Licensed Rights (defined below), You accept and agree
to be bound by the terms and conditions of this Creative Commons
Attribution-ShareAlike 4.0 International Public License ("Public
License"). To the extent this Public License may be interpreted as a
contract, You are granted the Licensed Rights in consideration of Your
acceptance of these terms and conditions, and the Licensor grants You
such rights in consideration of benefits the Licensor receives from
making the Licensed Material available under these terms and
conditions.
Section 1 -- Definitions.
a. Adapted Material means material subject to Copyright and Similar
Rights that is derived from or based upon the Licensed Material
and in which the Licensed Material is translated, altered,
arranged, transformed, or otherwise modified in a manner requiring
permission under the Copyright and Similar Rights held by the
Licensor. For purposes of this Public License, where the Licensed
Material is a musical work, performance, or sound recording,
Adapted Material is always produced where the Licensed Material is
synched in timed relation with a moving image.
b. Adapter's License means the license You apply to Your Copyright
and Similar Rights in Your contributions to Adapted Material in
accordance with the terms and conditions of this Public License.
c. BY-SA Compatible License means a license listed at
creativecommons.org/compatiblelicenses, approved by Creative
Commons as essentially the equivalent of this Public License.
d. Copyright and Similar Rights means copyright and/or similar rights
closely related to copyright including, without limitation,
performance, broadcast, sound recording, and Sui Generis Database
Rights, without regard to how the rights are labeled or
categorized. For purposes of this Public License, the rights
specified in Section 2(b)(1)-(2) are not Copyright and Similar
Rights.
e. Effective Technological Measures means those measures that, in the
absence of proper authority, may not be circumvented under laws
fulfilling obligations under Article 11 of the WIPO Copyright
Treaty adopted on December 20, 1996, and/or similar international
agreements.
f. Exceptions and Limitations means fair use, fair dealing, and/or
any other exception or limitation to Copyright and Similar Rights
that applies to Your use of the Licensed Material.
g. License Elements means the license attributes listed in the name
of a Creative Commons Public License. The License Elements of this
Public License are Attribution and ShareAlike.
h. Licensed Material means the artistic or literary work, database,
or other material to which the Licensor applied this Public
License.
i. Licensed Rights means the rights granted to You subject to the
terms and conditions of this Public License, which are limited to
all Copyright and Similar Rights that apply to Your use of the
Licensed Material and that the Licensor has authority to license.
j. Licensor means the individual(s) or entity(ies) granting rights
under this Public License.
k. Share means to provide material to the public by any means or
process that requires permission under the Licensed Rights, such
as reproduction, public display, public performance, distribution,
dissemination, communication, or importation, and to make material
available to the public including in ways that members of the
public may access the material from a place and at a time
individually chosen by them.
l. Sui Generis Database Rights means rights other than copyright
resulting from Directive 96/9/EC of the European Parliament and of
the Council of 11 March 1996 on the legal protection of databases,
as amended and/or succeeded, as well as other essentially
equivalent rights anywhere in the world.
m. You means the individual or entity exercising the Licensed Rights
under this Public License. Your has a corresponding meaning.
Section 2 -- Scope.
a. License grant.
1. Subject to the terms and conditions of this Public License,
the Licensor hereby grants You a worldwide, royalty-free,
non-sublicensable, non-exclusive, irrevocable license to
exercise the Licensed Rights in the Licensed Material to:
a. reproduce and Share the Licensed Material, in whole or
in part; and
b. produce, reproduce, and Share Adapted Material.
2. Exceptions and Limitations. For the avoidance of doubt, where
Exceptions and Limitations apply to Your use, this Public
License does not apply, and You do not need to comply with
its terms and conditions.
3. Term. The term of this Public License is specified in Section
6(a).
4. Media and formats; technical modifications allowed. The
Licensor authorizes You to exercise the Licensed Rights in
all media and formats whether now known or hereafter created,
and to make technical modifications necessary to do so. The
Licensor waives and/or agrees not to assert any right or
authority to forbid You from making technical modifications
necessary to exercise the Licensed Rights, including
technical modifications necessary to circumvent Effective
Technological Measures. For purposes of this Public License,
simply making modifications authorized by this Section 2(a)
(4) never produces Adapted Material.
5. Downstream recipients.
a. Offer from the Licensor -- Licensed Material. Every
recipient of the Licensed Material automatically
receives an offer from the Licensor to exercise the
Licensed Rights under the terms and conditions of this
Public License.
b. Additional offer from the Licensor -- Adapted Material.
Every recipient of Adapted Material from You
automatically receives an offer from the Licensor to
exercise the Licensed Rights in the Adapted Material
under the conditions of the Adapter's License You apply.
c. No downstream restrictions. You may not offer or impose
any additional or different terms or conditions on, or
apply any Effective Technological Measures to, the
Licensed Material if doing so restricts exercise of the
Licensed Rights by any recipient of the Licensed
Material.
6. No endorsement. Nothing in this Public License constitutes or
may be construed as permission to assert or imply that You
are, or that Your use of the Licensed Material is, connected
with, or sponsored, endorsed, or granted official status by,
the Licensor or others designated to receive attribution as
provided in Section 3(a)(1)(A)(i).
b. Other rights.
1. Moral rights, such as the right of integrity, are not
licensed under this Public License, nor are publicity,
privacy, and/or other similar personality rights; however, to
the extent possible, the Licensor waives and/or agrees not to
assert any such rights held by the Licensor to the limited
extent necessary to allow You to exercise the Licensed
Rights, but not otherwise.
2. Patent and trademark rights are not licensed under this
Public License.
3. To the extent possible, the Licensor waives any right to
collect royalties from You for the exercise of the Licensed
Rights, whether directly or through a collecting society
under any voluntary or waivable statutory or compulsory
licensing scheme. In all other cases the Licensor expressly
reserves any right to collect such royalties.
Section 3 -- License Conditions.
Your exercise of the Licensed Rights is expressly made subject to the
following conditions.
a. Attribution.
1. If You Share the Licensed Material (including in modified
form), You must:
a. retain the following if it is supplied by the Licensor
with the Licensed Material:
i. identification of the creator(s) of the Licensed
Material and any others designated to receive
attribution, in any reasonable manner requested by
the Licensor (including by pseudonym if
designated);
ii. a copyright notice;
iii. a notice that refers to this Public License;
iv. a notice that refers to the disclaimer of
warranties;
v. a URI or hyperlink to the Licensed Material to the
extent reasonably practicable;
b. indicate if You modified the Licensed Material and
retain an indication of any previous modifications; and
c. indicate the Licensed Material is licensed under this
Public License, and include the text of, or the URI or
hyperlink to, this Public License.
2. You may satisfy the conditions in Section 3(a)(1) in any
reasonable manner based on the medium, means, and context in
which You Share the Licensed Material. For example, it may be
reasonable to satisfy the conditions by providing a URI or
hyperlink to a resource that includes the required
information.
3. If requested by the Licensor, You must remove any of the
information required by Section 3(a)(1)(A) to the extent
reasonably practicable.
b. ShareAlike.
In addition to the conditions in Section 3(a), if You Share
Adapted Material You produce, the following conditions also apply.
1. The Adapter's License You apply must be a Creative Commons
license with the same License Elements, this version or
later, or a BY-SA Compatible License.
2. You must include the text of, or the URI or hyperlink to, the
Adapter's License You apply. You may satisfy this condition
in any reasonable manner based on the medium, means, and
context in which You Share Adapted Material.
3. You may not offer or impose any additional or different terms
or conditions on, or apply any Effective Technological
Measures to, Adapted Material that restrict exercise of the
rights granted under the Adapter's License You apply.
Section 4 -- Sui Generis Database Rights.
Where the Licensed Rights include Sui Generis Database Rights that
apply to Your use of the Licensed Material:
a. for the avoidance of doubt, Section 2(a)(1) grants You the right
to extract, reuse, reproduce, and Share all or a substantial
portion of the contents of the database;
b. if You include all or a substantial portion of the database
contents in a database in which You have Sui Generis Database
Rights, then the database in which You have Sui Generis Database
Rights (but not its individual contents) is Adapted Material,
including for purposes of Section 3(b); and
c. You must comply with the conditions in Section 3(a) if You Share
all or a substantial portion of the contents of the database.
For the avoidance of doubt, this Section 4 supplements and does not
replace Your obligations under this Public License where the Licensed
Rights include other Copyright and Similar Rights.
Section 5 -- Disclaimer of Warranties and Limitation of Liability.
a. UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE
EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS
AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF
ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS,
IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION,
WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS,
ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT
KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT
ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
b. TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE
TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION,
NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT,
INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES,
COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR
USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR
DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR
IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
c. The disclaimer of warranties and limitation of liability provided
above shall be interpreted in a manner that, to the extent
possible, most closely approximates an absolute disclaimer and
waiver of all liability.
Section 6 -- Term and Termination.
a. This Public License applies for the term of the Copyright and
Similar Rights licensed here. However, if You fail to comply with
this Public License, then Your rights under this Public License
terminate automatically.
b. Where Your right to use the Licensed Material has terminated under
Section 6(a), it reinstates:
1. automatically as of the date the violation is cured, provided
it is cured within 30 days of Your discovery of the
violation; or
2. upon express reinstatement by the Licensor.
For the avoidance of doubt, this Section 6(b) does not affect any
right the Licensor may have to seek remedies for Your violations
of this Public License.
c. For the avoidance of doubt, the Licensor may also offer the
Licensed Material under separate terms or conditions or stop
distributing the Licensed Material at any time; however, doing so
will not terminate this Public License.
d. Sections 1, 5, 6, 7, and 8 survive termination of this Public
License.
Section 7 -- Other Terms and Conditions.
a. The Licensor shall not be bound by any additional or different
terms or conditions communicated by You unless expressly agreed.
b. Any arrangements, understandings, or agreements regarding the
Licensed Material not stated herein are separate from and
independent of the terms and conditions of this Public License.
Section 8 -- Interpretation.
a. For the avoidance of doubt, this Public License does not, and
shall not be interpreted to, reduce, limit, restrict, or impose
conditions on any use of the Licensed Material that could lawfully
be made without permission under this Public License.
b. To the extent possible, if any provision of this Public License is
deemed unenforceable, it shall be automatically reformed to the
minimum extent necessary to make it enforceable. If the provision
cannot be reformed, it shall be severed from this Public License
without affecting the enforceability of the remaining terms and
conditions.
c. No term or condition of this Public License will be waived and no
failure to comply consented to unless expressly agreed to by the
Licensor.
d. Nothing in this Public License constitutes or may be interpreted
as a limitation upon, or waiver of, any privileges and immunities
that apply to the Licensor or You, including from the legal
processes of any jurisdiction or authority.
=======================================================================
Creative Commons is not a party to its public
licenses. Notwithstanding, Creative Commons may elect to apply one of
its public licenses to material it publishes and in those instances
will be considered the “Licensor.” The text of the Creative Commons
public licenses is dedicated to the public domain under the CC0 Public
Domain Dedication. Except for the limited purpose of indicating that
material is shared under a Creative Commons public license or as
otherwise permitted by the Creative Commons policies published at
creativecommons.org/policies, Creative Commons does not authorize the
use of the trademark "Creative Commons" or any other trademark or logo
of Creative Commons without its prior written consent including,
without limitation, in connection with any unauthorized modifications
to any of its public licenses or any other arrangements,
understandings, or agreements concerning use of licensed material. For
the avoidance of doubt, this paragraph does not form part of the
public licenses.
Creative Commons may be contacted at creativecommons.org.

View File

@ -1,2 +1,9 @@
# DISCRETE TTL FPGA
WIP.
Building an FPGA from 74-series logic ICs. For fun and education.
## License
TTL-FPGA, Copyright (C) 2019 Markus Koch <markus@notsyncing.net>
This work is released under a [Creative Commons Attribution-ShareAlike 4.0 International license](https://creativecommons.org/licenses/by-sa/4.0/).
You can find a copy of the full license in [LICENSE.txt](./LICENSE.txt).

BIN
doc/lut-helper.ods Normal file

Binary file not shown.

12
doc/notes.md Normal file
View File

@ -0,0 +1,12 @@
# Intro
* Technology is becoming more complex every day.
* Devices get smaller, integration gets higher
* As such, it has become harder to actually understand how the devices work.
* 80s, you could open your PC and start probing signals on the mainboard to understand which instructions a CPU executed. These days, pretty much everything can be integrated into a single chip and the actual functionality is *built* in software.
* One example of such a highly integrated component is the FPGA.
* FPGAs essentially allow the designer to create large digital designs inside of an IC.
* As these designs are created by writing software-like source code, one might easily forget the fact that what is created is, indeed, a digital circuit.
* There is no PCB, no components, but also no visibility of the individual building blocks and connections between them.
* To aid students learning about FPGAs better understand the technology, this project aims to provide a platform to look at the inner workings of such a chip by breaking it out of the IC and bringing it onto a PCB where every signal can be traced and measured.

File diff suppressed because it is too large Load Diff

View File

@ -7,7 +7,7 @@ encoding utf-8
Sheet 3 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "01"
Rev "02"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "Logic Block"
Comment2 "single 4-input LUT / dual 3-input LUT"
@ -19,10 +19,10 @@ L 74xx_IEEE:74164 U?
U 1 1 5CF42176
P 3100 3450
AR Path="/5CF41639/5CF42176" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF42176" Ref="U?" Part="1"
F 0 "U?" H 3450 3650 50 0000 C CNN
AR Path="/5D77FDBE/5D7AF013/5CF42176" Ref="U13" Part="1"
F 0 "U13" H 3450 3650 50 0000 C CNN
F 1 "74164" H 3500 3750 50 0000 C CNN
F 2 "" H 3100 3450 50 0001 C CNN
F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 3100 3450 50 0001 C CNN
F 3 "" H 3100 3450 50 0001 C CNN
1 3100 3450
1 0 0 -1
@ -32,10 +32,10 @@ L 74xx_IEEE:74164 U?
U 1 1 5CF427E5
P 3100 5000
AR Path="/5CF41639/5CF427E5" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF427E5" Ref="U?" Part="1"
F 0 "U?" H 3450 5200 50 0000 C CNN
AR Path="/5D77FDBE/5D7AF013/5CF427E5" Ref="U17" Part="1"
F 0 "U17" H 3450 5200 50 0000 C CNN
F 1 "74164" H 3500 5300 50 0000 C CNN
F 2 "" H 3100 5000 50 0001 C CNN
F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 3100 5000 50 0001 C CNN
F 3 "" H 3100 5000 50 0001 C CNN
1 3100 5000
1 0 0 -1
@ -103,10 +103,10 @@ L 74xx_IEEE:74251 U?
U 1 1 5CF5B900
P 4800 5200
AR Path="/5CF41639/5CF5B900" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF5B900" Ref="U?" Part="1"
F 0 "U?" H 5000 5900 50 0000 C CNN
AR Path="/5D77FDBE/5D7AF013/5CF5B900" Ref="U18" Part="1"
F 0 "U18" H 5000 5900 50 0000 C CNN
F 1 "74251" H 4700 5900 50 0000 C CNN
F 2 "" H 4800 5200 50 0001 C CNN
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 4800 5200 50 0001 C CNN
F 3 "" H 4800 5200 50 0001 C CNN
1 4800 5200
1 0 0 -1
@ -144,10 +144,10 @@ L 74xx_IEEE:74251 U?
U 1 1 5CF4F8AB
P 4800 3650
AR Path="/5CF41639/5CF4F8AB" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF4F8AB" Ref="U?" Part="1"
F 0 "U?" H 5000 4350 50 0000 C CNN
AR Path="/5D77FDBE/5D7AF013/5CF4F8AB" Ref="U14" Part="1"
F 0 "U14" H 5000 4350 50 0000 C CNN
F 1 "74251" H 4700 4350 50 0000 C CNN
F 2 "" H 4800 3650 50 0001 C CNN
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 4800 3650 50 0001 C CNN
F 3 "" H 4800 3650 50 0001 C CNN
1 4800 3650
1 0 0 -1
@ -192,7 +192,7 @@ Wire Wire Line
Text HLabel 2000 5950 0 50 Output ~ 0
isp_miso
Text HLabel 2000 2700 0 50 Input ~ 0
lut_in
lut_in[3..0]
Text Label 3950 3200 0 50 ~ 0
lut_in0
Text Label 2050 2700 0 50 ~ 0
@ -213,8 +213,8 @@ L power:GNDD #PWR?
U 1 1 5D015E6D
P 6200 4550
AR Path="/5CF41639/5D015E6D" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D015E6D" Ref="#PWR0129" Part="1"
F 0 "#PWR0129" H 6200 4300 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D015E6D" Ref="#PWR065" Part="1"
F 0 "#PWR065" H 6200 4300 50 0001 C CNN
F 1 "GNDD" H 6204 4395 50 0000 C CNN
F 2 "" H 6200 4550 50 0001 C CNN
F 3 "" H 6200 4550 50 0001 C CNN
@ -250,10 +250,10 @@ L 74xx_IEEE:74157 U?
U 1 1 5D187D09
P 9050 4150
AR Path="/5CF41639/5D187D09" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D187D09" Ref="U?" Part="1"
F 0 "U?" H 9400 4500 50 0000 C CNN
AR Path="/5D77FDBE/5D7AF013/5D187D09" Ref="U15" Part="1"
F 0 "U15" H 9400 4500 50 0000 C CNN
F 1 "74157" H 9450 4600 50 0000 C CNN
F 2 "" H 9050 4150 50 0001 C CNN
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 9050 4150 50 0001 C CNN
F 3 "" H 9050 4150 50 0001 C CNN
1 9050 4150
1 0 0 -1
@ -263,10 +263,10 @@ L 74xx:74LS174 U?
U 1 1 5CF941AD
P 6950 4400
AR Path="/5CF41639/5CF941AD" Ref="U?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF941AD" Ref="U?" Part="1"
F 0 "U?" H 7200 4950 50 0000 C CNN
AR Path="/5D77FDBE/5D7AF013/5CF941AD" Ref="U16" Part="1"
F 0 "U16" H 7200 4950 50 0000 C CNN
F 1 "74LS174" H 6750 4950 50 0000 C CNN
F 2 "" H 6950 4400 50 0001 C CNN
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 6950 4400 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS174" H 6950 4400 50 0001 C CNN
1 6950 4400
1 0 0 -1
@ -309,10 +309,10 @@ L Device:R R?
U 1 1 5D1A7947
P 5550 4350
AR Path="/5CF41639/5D1A7947" Ref="R?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D1A7947" Ref="R?" Part="1"
F 0 "R?" H 5480 4304 50 0000 R CNN
AR Path="/5D77FDBE/5D7AF013/5D1A7947" Ref="R16" Part="1"
F 0 "R16" H 5480 4304 50 0000 R CNN
F 1 "10k" H 5480 4395 50 0000 R CNN
F 2 "" V 5480 4350 50 0001 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 5480 4350 50 0001 C CNN
F 3 "~" H 5550 4350 50 0001 C CNN
1 5550 4350
1 0 0 1
@ -322,8 +322,8 @@ L power:GNDD #PWR?
U 1 1 5D1A7DBD
P 5550 4600
AR Path="/5CF41639/5D1A7DBD" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D1A7DBD" Ref="#PWR0130" Part="1"
F 0 "#PWR0130" H 5550 4350 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D1A7DBD" Ref="#PWR066" Part="1"
F 0 "#PWR066" H 5550 4350 50 0001 C CNN
F 1 "GNDD" H 5554 4445 50 0000 C CNN
F 2 "" H 5550 4600 50 0001 C CNN
F 3 "" H 5550 4600 50 0001 C CNN
@ -405,8 +405,8 @@ L power:GNDD #PWR?
U 1 1 5D26A4EB
P 6950 5300
AR Path="/5CF41639/5D26A4EB" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D26A4EB" Ref="#PWR0132" Part="1"
F 0 "#PWR0132" H 6950 5050 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D26A4EB" Ref="#PWR068" Part="1"
F 0 "#PWR068" H 6950 5050 50 0001 C CNN
F 1 "GNDD" H 6954 5145 50 0000 C CNN
F 2 "" H 6950 5300 50 0001 C CNN
F 3 "" H 6950 5300 50 0001 C CNN
@ -420,8 +420,8 @@ L power:GNDD #PWR?
U 1 1 5D276079
P 8300 3550
AR Path="/5CF41639/5D276079" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D276079" Ref="#PWR0133" Part="1"
F 0 "#PWR0133" H 8300 3300 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D276079" Ref="#PWR058" Part="1"
F 0 "#PWR058" H 8300 3300 50 0001 C CNN
F 1 "GNDD" H 8304 3395 50 0000 C CNN
F 2 "" H 8300 3550 50 0001 C CNN
F 3 "" H 8300 3550 50 0001 C CNN
@ -439,8 +439,8 @@ L power:VCC #PWR?
U 1 1 5D27AEF5
P 6950 3600
AR Path="/5CF41639/5D27AEF5" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D27AEF5" Ref="#PWR0134" Part="1"
F 0 "#PWR0134" H 6950 3450 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D27AEF5" Ref="#PWR060" Part="1"
F 0 "#PWR060" H 6950 3450 50 0001 C CNN
F 1 "VCC" H 6967 3773 50 0000 C CNN
F 2 "" H 6950 3600 50 0001 C CNN
F 3 "" H 6950 3600 50 0001 C CNN
@ -454,8 +454,8 @@ L power:GNDD #PWR?
U 1 1 5D2924B9
P 4800 6000
AR Path="/5CF41639/5D2924B9" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2924B9" Ref="#PWR0135" Part="1"
F 0 "#PWR0135" H 4800 5750 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2924B9" Ref="#PWR069" Part="1"
F 0 "#PWR069" H 4800 5750 50 0001 C CNN
F 1 "GNDD" H 4804 5845 50 0000 C CNN
F 2 "" H 4800 6000 50 0001 C CNN
F 3 "" H 4800 6000 50 0001 C CNN
@ -469,8 +469,8 @@ L power:GNDD #PWR?
U 1 1 5D2970E5
P 4450 4400
AR Path="/5CF41639/5D2970E5" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2970E5" Ref="#PWR0136" Part="1"
F 0 "#PWR0136" H 4450 4150 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2970E5" Ref="#PWR061" Part="1"
F 0 "#PWR061" H 4450 4150 50 0001 C CNN
F 1 "GNDD" H 4454 4245 50 0000 C CNN
F 2 "" H 4450 4400 50 0001 C CNN
F 3 "" H 4450 4400 50 0001 C CNN
@ -486,8 +486,8 @@ L power:VCC #PWR?
U 1 1 5D29AD03
P 5150 4450
AR Path="/5CF41639/5D29AD03" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D29AD03" Ref="#PWR0137" Part="1"
F 0 "#PWR0137" H 5150 4300 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D29AD03" Ref="#PWR063" Part="1"
F 0 "#PWR063" H 5150 4300 50 0001 C CNN
F 1 "VCC" H 5167 4623 50 0000 C CNN
F 2 "" H 5150 4450 50 0001 C CNN
F 3 "" H 5150 4450 50 0001 C CNN
@ -503,8 +503,8 @@ L power:VCC #PWR?
U 1 1 5D29EA17
P 4800 2900
AR Path="/5CF41639/5D29EA17" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D29EA17" Ref="#PWR0138" Part="1"
F 0 "#PWR0138" H 4800 2750 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D29EA17" Ref="#PWR054" Part="1"
F 0 "#PWR054" H 4800 2750 50 0001 C CNN
F 1 "VCC" H 4817 3073 50 0000 C CNN
F 2 "" H 4800 2900 50 0001 C CNN
F 3 "" H 4800 2900 50 0001 C CNN
@ -518,8 +518,8 @@ L power:GNDD #PWR?
U 1 1 5D2B29AB
P 2900 2850
AR Path="/5CF41639/5D2B29AB" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2B29AB" Ref="#PWR0139" Part="1"
F 0 "#PWR0139" H 2900 2600 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2B29AB" Ref="#PWR053" Part="1"
F 0 "#PWR053" H 2900 2600 50 0001 C CNN
F 1 "GNDD" H 2904 2695 50 0000 C CNN
F 2 "" H 2900 2850 50 0001 C CNN
F 3 "" H 2900 2850 50 0001 C CNN
@ -537,8 +537,8 @@ L power:VCC #PWR?
U 1 1 5D2B7E69
P 3300 3000
AR Path="/5CF41639/5D2B7E69" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2B7E69" Ref="#PWR0140" Part="1"
F 0 "#PWR0140" H 3300 2850 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2B7E69" Ref="#PWR055" Part="1"
F 0 "#PWR055" H 3300 2850 50 0001 C CNN
F 1 "VCC" H 3317 3173 50 0000 C CNN
F 2 "" H 3300 3000 50 0001 C CNN
F 3 "" H 3300 3000 50 0001 C CNN
@ -554,8 +554,8 @@ L power:GNDD #PWR?
U 1 1 5D2CD01F
P 2900 4450
AR Path="/5CF41639/5D2CD01F" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2CD01F" Ref="#PWR0141" Part="1"
F 0 "#PWR0141" H 2900 4200 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2CD01F" Ref="#PWR062" Part="1"
F 0 "#PWR062" H 2900 4200 50 0001 C CNN
F 1 "GNDD" H 2904 4295 50 0000 C CNN
F 2 "" H 2900 4450 50 0001 C CNN
F 3 "" H 2900 4450 50 0001 C CNN
@ -571,8 +571,8 @@ L power:VCC #PWR?
U 1 1 5D2D1794
P 3300 4550
AR Path="/5CF41639/5D2D1794" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2D1794" Ref="#PWR0142" Part="1"
F 0 "#PWR0142" H 3300 4400 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2D1794" Ref="#PWR064" Part="1"
F 0 "#PWR064" H 3300 4400 50 0001 C CNN
F 1 "VCC" H 3317 4723 50 0000 C CNN
F 2 "" H 3300 4550 50 0001 C CNN
F 3 "" H 3300 4550 50 0001 C CNN
@ -602,9 +602,9 @@ L power:GNDD #PWR?
U 1 1 5CF3ABB3
P 8850 3450
AR Path="/5CF41639/5CF3ABB3" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF3ABB3" Ref="#PWR0144" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF3ABB3" Ref="#PWR057" Part="1"
AR Path="/5D77FDBE/5CF3ABB3" Ref="#PWR?" Part="1"
F 0 "#PWR0144" H 8850 3200 50 0001 C CNN
F 0 "#PWR057" H 8850 3200 50 0001 C CNN
F 1 "GNDD" H 8854 3295 50 0000 C CNN
F 2 "" H 8850 3450 50 0001 C CNN
F 3 "" H 8850 3450 50 0001 C CNN
@ -620,9 +620,9 @@ L power:VCC #PWR?
U 1 1 5CF3ABBB
P 9200 3550
AR Path="/5CF41639/5CF3ABBB" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF3ABBB" Ref="#PWR0145" Part="1"
AR Path="/5D77FDBE/5D7AF013/5CF3ABBB" Ref="#PWR059" Part="1"
AR Path="/5D77FDBE/5CF3ABBB" Ref="#PWR?" Part="1"
F 0 "#PWR0145" H 9200 3400 50 0001 C CNN
F 0 "#PWR059" H 9200 3400 50 0001 C CNN
F 1 "VCC" H 9217 3723 50 0000 C CNN
F 2 "" H 9200 3550 50 0001 C CNN
F 3 "" H 9200 3550 50 0001 C CNN
@ -636,10 +636,10 @@ L Device:C C?
U 1 1 5D2EACB1
P 9500 2050
AR Path="/5D77FDBE/5D2EACB1" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACB1" Ref="C?" Part="1"
F 0 "C?" H 9500 2150 50 0000 L CNN
AR Path="/5D77FDBE/5D7AF013/5D2EACB1" Ref="C16" Part="1"
F 0 "C16" H 9500 2150 50 0000 L CNN
F 1 "100n" H 9500 1950 50 0000 L CNN
F 2 "" H 9538 1900 50 0001 C CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9538 1900 50 0001 C CNN
F 3 "~" H 9500 2050 50 0001 C CNN
1 9500 2050
1 0 0 -1
@ -649,10 +649,10 @@ L Device:C C?
U 1 1 5D2EACB7
P 9700 2050
AR Path="/5D77FDBE/5D2EACB7" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACB7" Ref="C?" Part="1"
F 0 "C?" H 9700 2150 50 0000 L CNN
AR Path="/5D77FDBE/5D7AF013/5D2EACB7" Ref="C17" Part="1"
F 0 "C17" H 9700 2150 50 0000 L CNN
F 1 "100n" H 9700 1950 50 0000 L CNN
F 2 "" H 9738 1900 50 0001 C CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9738 1900 50 0001 C CNN
F 3 "~" H 9700 2050 50 0001 C CNN
1 9700 2050
1 0 0 -1
@ -662,10 +662,10 @@ L Device:C C?
U 1 1 5D2EACBD
P 9900 2050
AR Path="/5D77FDBE/5D2EACBD" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACBD" Ref="C?" Part="1"
F 0 "C?" H 9900 2150 50 0000 L CNN
AR Path="/5D77FDBE/5D7AF013/5D2EACBD" Ref="C18" Part="1"
F 0 "C18" H 9900 2150 50 0000 L CNN
F 1 "100n" H 9900 1950 50 0000 L CNN
F 2 "" H 9938 1900 50 0001 C CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9938 1900 50 0001 C CNN
F 3 "~" H 9900 2050 50 0001 C CNN
1 9900 2050
1 0 0 -1
@ -675,10 +675,10 @@ L Device:C C?
U 1 1 5D2EACC3
P 10100 2050
AR Path="/5D77FDBE/5D2EACC3" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACC3" Ref="C?" Part="1"
F 0 "C?" H 10100 2150 50 0000 L CNN
AR Path="/5D77FDBE/5D7AF013/5D2EACC3" Ref="C19" Part="1"
F 0 "C19" H 10100 2150 50 0000 L CNN
F 1 "100n" H 10100 1950 50 0000 L CNN
F 2 "" H 10138 1900 50 0001 C CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 10138 1900 50 0001 C CNN
F 3 "~" H 10100 2050 50 0001 C CNN
1 10100 2050
1 0 0 -1
@ -716,8 +716,8 @@ L power:GNDD #PWR?
U 1 1 5D2EACE7
P 9700 2400
AR Path="/5D77FDBE/5D2EACE7" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACE7" Ref="#PWR0147" Part="1"
F 0 "#PWR0147" H 9700 2150 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2EACE7" Ref="#PWR052" Part="1"
F 0 "#PWR052" H 9700 2150 50 0001 C CNN
F 1 "GNDD" H 9704 2245 50 0000 C CNN
F 2 "" H 9700 2400 50 0001 C CNN
F 3 "" H 9700 2400 50 0001 C CNN
@ -729,10 +729,10 @@ L Device:C C?
U 1 1 5D2FCD73
P 10300 2050
AR Path="/5D77FDBE/5D2FCD73" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2FCD73" Ref="C?" Part="1"
F 0 "C?" H 10300 2150 50 0000 L CNN
AR Path="/5D77FDBE/5D7AF013/5D2FCD73" Ref="C20" Part="1"
F 0 "C20" H 10300 2150 50 0000 L CNN
F 1 "100n" H 10300 1950 50 0000 L CNN
F 2 "" H 10338 1900 50 0001 C CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 10338 1900 50 0001 C CNN
F 3 "~" H 10300 2050 50 0001 C CNN
1 10300 2050
1 0 0 -1
@ -742,10 +742,10 @@ L Device:C C?
U 1 1 5D2FCFE7
P 9300 2050
AR Path="/5D77FDBE/5D2FCFE7" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2FCFE7" Ref="C?" Part="1"
F 0 "C?" H 9300 2150 50 0000 L CNN
AR Path="/5D77FDBE/5D7AF013/5D2FCFE7" Ref="C15" Part="1"
F 0 "C15" H 9300 2150 50 0000 L CNN
F 1 "100n" H 9300 1950 50 0000 L CNN
F 2 "" H 9338 1900 50 0001 C CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9338 1900 50 0001 C CNN
F 3 "~" H 9300 2050 50 0001 C CNN
1 9300 2050
1 0 0 -1
@ -785,10 +785,10 @@ L Device:C C?
U 1 1 5D182B36
P 9100 2050
AR Path="/5D77FDBE/5D182B36" Ref="C?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D182B36" Ref="C?" Part="1"
F 0 "C?" H 9100 2150 50 0000 L CNN
AR Path="/5D77FDBE/5D7AF013/5D182B36" Ref="C14" Part="1"
F 0 "C14" H 9100 2150 50 0000 L CNN
F 1 "100n" H 9100 1950 50 0000 L CNN
F 2 "" H 9138 1900 50 0001 C CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9138 1900 50 0001 C CNN
F 3 "~" H 9100 2050 50 0001 C CNN
1 9100 2050
1 0 0 -1
@ -808,8 +808,8 @@ L power:VCC #PWR?
U 1 1 5D2EACE1
P 9700 1700
AR Path="/5D77FDBE/5D2EACE1" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D2EACE1" Ref="#PWR0146" Part="1"
F 0 "#PWR0146" H 9700 1550 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D2EACE1" Ref="#PWR051" Part="1"
F 0 "#PWR051" H 9700 1550 50 0001 C CNN
F 1 "VCC" H 9717 1873 50 0000 C CNN
F 2 "" H 9700 1700 50 0001 C CNN
F 3 "" H 9700 1700 50 0001 C CNN
@ -837,12 +837,12 @@ lut_in3_n
Text Label 3950 2150 2 50 ~ 0
lut_b_en_n
$Comp
L Device:R R?
L Device:R R15
U 1 1 5D4D5C26
P 4150 2150
F 0 "R?" H 4220 2196 50 0000 L CNN
F 0 "R15" H 4220 2196 50 0000 L CNN
F 1 "10k" H 4220 2105 50 0000 L CNN
F 2 "" V 4080 2150 50 0001 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 4080 2150 50 0001 C CNN
F 3 "~" H 4150 2150 50 0001 C CNN
1 4150 2150
1 0 0 -1
@ -859,12 +859,12 @@ Wire Wire Line
Wire Wire Line
4150 2400 3950 2400
$Comp
L Device:D_Schottky D?
L Device:D_Schottky D11
U 1 1 5D50C782
P 3800 2400
F 0 "D?" H 3800 2500 50 0000 C CNN
F 0 "D11" H 3800 2500 50 0000 C CNN
F 1 "D_Schottky" H 3800 2300 50 0000 C CNN
F 2 "" H 3800 2400 50 0001 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 3800 2400 50 0001 C CNN
F 3 "~" H 3800 2400 50 0001 C CNN
1 3800 2400
1 0 0 -1
@ -874,23 +874,23 @@ Wire Wire Line
Text Label 4550 2400 2 50 ~ 0
lut_a_en_n
$Comp
L Device:R R?
L Device:R R14
U 1 1 5D544A69
P 3500 1900
F 0 "R?" H 3570 1946 50 0000 L CNN
F 0 "R14" H 3570 1946 50 0000 L CNN
F 1 "10k" H 3570 1855 50 0000 L CNN
F 2 "" V 3430 1900 50 0001 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 3430 1900 50 0001 C CNN
F 3 "~" H 3500 1900 50 0001 C CNN
1 3500 1900
1 0 0 -1
$EndComp
$Comp
L Device:D_Schottky D?
L Device:D_Schottky D10
U 1 1 5D544D70
P 3150 2150
F 0 "D?" H 3150 2250 50 0000 C CNN
F 0 "D10" H 3150 2250 50 0000 C CNN
F 1 "D_Schottky" H 3150 2050 50 0000 C CNN
F 2 "" H 3150 2150 50 0001 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 3150 2150 50 0001 C CNN
F 3 "~" H 3150 2150 50 0001 C CNN
1 3150 2150
1 0 0 -1
@ -916,8 +916,8 @@ L power:VCC #PWR?
U 1 1 5D6F060A
P 2450 3100
AR Path="/5CF41639/5D6F060A" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D6F060A" Ref="#PWR?" Part="1"
F 0 "#PWR?" H 2450 2950 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D6F060A" Ref="#PWR056" Part="1"
F 0 "#PWR056" H 2450 2950 50 0001 C CNN
F 1 "VCC" H 2467 3273 50 0000 C CNN
F 2 "" H 2450 3100 50 0001 C CNN
F 3 "" H 2450 3100 50 0001 C CNN
@ -933,8 +933,8 @@ L power:VCC #PWR?
U 1 1 5D6F756A
P 2550 4650
AR Path="/5CF41639/5D6F756A" Ref="#PWR?" Part="1"
AR Path="/5D77FDBE/5D7AF013/5D6F756A" Ref="#PWR?" Part="1"
F 0 "#PWR?" H 2550 4500 50 0001 C CNN
AR Path="/5D77FDBE/5D7AF013/5D6F756A" Ref="#PWR067" Part="1"
F 0 "#PWR067" H 2550 4500 50 0001 C CNN
F 1 "VCC" H 2567 4823 50 0000 C CNN
F 2 "" H 2550 4650 50 0001 C CNN
F 3 "" H 2550 4650 50 0001 C CNN
@ -944,23 +944,23 @@ $EndComp
Wire Wire Line
2550 4650 2550 4750
$Comp
L Device:D_Schottky D?
L Device:D_Schottky D12
U 1 1 5D7F6986
P 5800 3650
F 0 "D?" H 5800 3750 50 0000 C CNN
F 0 "D12" H 5800 3750 50 0000 C CNN
F 1 "D_Schottky" H 5800 3550 50 0000 C CNN
F 2 "" H 5800 3650 50 0001 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 5800 3650 50 0001 C CNN
F 3 "~" H 5800 3650 50 0001 C CNN
1 5800 3650
0 -1 -1 0
$EndComp
$Comp
L Device:D_Schottky D?
L Device:D_Schottky D13
U 1 1 5D7F6FF8
P 5800 4500
F 0 "D?" H 5800 4600 50 0000 C CNN
F 0 "D13" H 5800 4600 50 0000 C CNN
F 1 "D_Schottky" H 5800 4400 50 0000 C CNN
F 2 "" H 5800 4500 50 0001 C CNN
F 2 "Diode_SMD:D_0603_1608Metric" H 5800 4500 50 0001 C CNN
F 3 "~" H 5800 4500 50 0001 C CNN
1 5800 4500
0 1 1 0

View File

@ -325,6 +325,26 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Schottky
#
DEF Device_D_Schottky D 0 40 N N 1 F N

View File

@ -1,4 +1,4 @@
update=Thu 30 May 2019 02:28:07 PM CEST
update=Sat 01 Jun 2019 09:25:42 PM CEST
version=1
last_client=kicad
[general]
@ -22,15 +22,15 @@ AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinTrackWidth=0.1524
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
TrackWidth1=0.1524
ViaDiameter1=0.6
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
@ -57,7 +57,7 @@ OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
@ -223,14 +223,14 @@ Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=1
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2

View File

@ -7,7 +7,7 @@ encoding utf-8
Sheet 1 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "01"
Rev "02"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "PCB"
Comment2 ""
@ -19,10 +19,10 @@ Wire Wire Line
Wire Wire Line
7900 3350 7900 3250
$Comp
L power:VCC #PWR?
L power:VCC #PWR04
U 1 1 5FF9C392
P 7900 3250
F 0 "#PWR?" H 7900 3100 50 0001 C CNN
F 0 "#PWR04" H 7900 3100 50 0001 C CNN
F 1 "VCC" H 7917 3423 50 0000 C CNN
F 2 "" H 7900 3250 50 0001 C CNN
F 3 "" H 7900 3250 50 0001 C CNN
@ -30,10 +30,10 @@ F 3 "" H 7900 3250 50 0001 C CNN
-1 0 0 -1
$EndComp
$Comp
L power:GNDD #PWR?
L power:GNDD #PWR06
U 1 1 5FF9C39C
P 7800 3450
F 0 "#PWR?" H 7800 3200 50 0001 C CNN
F 0 "#PWR06" H 7800 3200 50 0001 C CNN
F 1 "GNDD" V 7804 3340 50 0000 R CNN
F 2 "" H 7800 3450 50 0001 C CNN
F 3 "" H 7800 3450 50 0001 C CNN
@ -164,10 +164,10 @@ Wire Wire Line
Wire Wire Line
3550 3450 3350 3450
$Comp
L power:GNDD #PWR?
L power:GNDD #PWR05
U 1 1 5FE8BD0F
P 3550 3450
F 0 "#PWR?" H 3550 3200 50 0001 C CNN
F 0 "#PWR05" H 3550 3200 50 0001 C CNN
F 1 "GNDD" V 3554 3340 50 0000 R CNN
F 2 "" H 3550 3450 50 0001 C CNN
F 3 "" H 3550 3450 50 0001 C CNN
@ -175,10 +175,10 @@ F 3 "" H 3550 3450 50 0001 C CNN
0 -1 -1 0
$EndComp
$Comp
L power:VCC #PWR?
L power:VCC #PWR03
U 1 1 5FE8B843
P 3450 3250
F 0 "#PWR?" H 3450 3100 50 0001 C CNN
F 0 "#PWR03" H 3450 3100 50 0001 C CNN
F 1 "VCC" H 3467 3423 50 0000 C CNN
F 2 "" H 3450 3250 50 0001 C CNN
F 3 "" H 3450 3250 50 0001 C CNN
@ -189,17 +189,6 @@ Wire Wire Line
3450 3350 3450 3250
Wire Wire Line
3350 3350 3450 3350
$Comp
L Connector:Conn_01x12_Female J?
U 1 1 5FE88CA2
P 3150 3850
F 0 "J?" H 3100 4450 50 0000 C CNN
F 1 "Left" H 3050 3200 50 0000 C CNN
F 2 "" H 3150 3850 50 0001 C CNN
F 3 "~" H 3150 3850 50 0001 C CNN
1 3150 3850
-1 0 0 -1
$EndComp
Wire Wire Line
6800 3400 7100 3400
Text Label 3950 4550 0 50 ~ 0
@ -217,10 +206,10 @@ VCC\nGND\nCLK\nRST\nSCK\nmiso\nmosi\n\nI0\nI1\nI2\nI3
Wire Wire Line
5250 5600 5250 5550
$Comp
L power:VCC #PWR?
L power:VCC #PWR012
U 1 1 60046AFF
P 5250 5550
F 0 "#PWR?" H 5250 5400 50 0001 C CNN
F 0 "#PWR012" H 5250 5400 50 0001 C CNN
F 1 "VCC" H 5150 5650 50 0000 C CNN
F 2 "" H 5250 5550 50 0001 C CNN
F 3 "" H 5250 5550 50 0001 C CNN
@ -228,10 +217,10 @@ F 3 "" H 5250 5550 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L power:GNDD #PWR?
L power:GNDD #PWR09
U 1 1 60046AF5
P 5200 5200
F 0 "#PWR?" H 5200 4950 50 0001 C CNN
F 0 "#PWR09" H 5200 4950 50 0001 C CNN
F 1 "GNDD" H 5204 5045 50 0000 C CNN
F 2 "" H 5200 5200 50 0001 C CNN
F 3 "" H 5200 5200 50 0001 C CNN
@ -307,23 +296,23 @@ Wire Wire Line
Text Notes 6400 5850 3 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI0\nI1\nI2\nI3
$Comp
L Connector:Conn_01x12_Female J?
L Connector:Conn_01x12_Female J4
U 1 1 60090C3D
P 5750 1850
F 0 "J?" H 5700 2450 50 0000 C CNN
F 1 "Top" V 5650 1150 50 0000 C CNN
F 2 "" H 5750 1850 50 0001 C CNN
F 3 "~" H 5750 1850 50 0001 C CNN
1 5750 1850
0 -1 -1 0
P 5750 5800
F 0 "J4" H 5700 6400 50 0000 C CNN
F 1 "Bottom" V 5650 5050 50 0000 C CNN
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 5750 5800 50 0001 C CNN
F 3 "~" H 5750 5800 50 0001 C CNN
1 5750 5800
0 -1 1 0
$EndComp
Text Notes 6400 1800 1 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI0\nI1\nI2\nI3
$Comp
L power:VCC #PWR?
L power:VCC #PWR01
U 1 1 600A7963
P 5150 2150
F 0 "#PWR?" H 5150 2000 50 0001 C CNN
F 0 "#PWR01" H 5150 2000 50 0001 C CNN
F 1 "VCC" H 5250 2200 50 0000 C CNN
F 2 "" H 5150 2150 50 0001 C CNN
F 3 "" H 5150 2150 50 0001 C CNN
@ -450,10 +439,10 @@ Wire Wire Line
Wire Wire Line
5350 2250 5350 2050
$Comp
L power:GNDD #PWR?
L power:GNDD #PWR02
U 1 1 600A7959
P 5350 2250
F 0 "#PWR?" H 5350 2000 50 0001 C CNN
F 0 "#PWR02" H 5350 2000 50 0001 C CNN
F 1 "GNDD" H 5354 2095 50 0000 C CNN
F 2 "" H 5350 2250 50 0001 C CNN
F 3 "" H 5350 2250 50 0001 C CNN
@ -476,27 +465,135 @@ Wire Notes Line
Wire Notes Line
3150 5800 3150 1850
$Comp
L Connector:Conn_01x12_Male J?
L Connector:Conn_01x12_Male J1
U 1 1 5CF30EFB
P 5750 1850
F 0 "J1" H 5850 2450 50 0000 R CNN
F 1 "Top" V 5850 1200 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 5750 1850 50 0001 C CNN
F 3 "~" H 5750 1850 50 0001 C CNN
1 5750 1850
0 -1 1 0
$EndComp
$Comp
L Connector:Conn_01x12_Male J3
U 1 1 5CF23FEF
P 8200 3850
F 0 "J?" H 8300 4450 50 0000 R CNN
F 0 "J3" H 8300 4450 50 0000 R CNN
F 1 "Right" H 8400 3200 50 0000 R CNN
F 2 "" H 8200 3850 50 0001 C CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 8200 3850 50 0001 C CNN
F 3 "~" H 8200 3850 50 0001 C CNN
1 8200 3850
-1 0 0 -1
$EndComp
$Comp
L Connector:Conn_01x12_Male J?
U 1 1 5CF30EFB
P 5750 5800
F 0 "J?" H 5850 6400 50 0000 R CNN
F 1 "Bottom" V 5850 5150 50 0000 R CNN
F 2 "" H 5750 5800 50 0001 C CNN
F 3 "~" H 5750 5800 50 0001 C CNN
1 5750 5800
L Connector:Conn_01x12_Female J2
U 1 1 5FE88CA2
P 3150 3850
F 0 "J2" H 3100 4450 50 0000 C CNN
F 1 "Left" H 3050 3200 50 0000 C CNN
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 3150 3850 50 0001 C CNN
F 3 "~" H 3150 3850 50 0001 C CNN
1 3150 3850
-1 0 0 -1
$EndComp
$Comp
L Device:CP C1
U 1 1 5CF70F0E
P 3550 5150
F 0 "C1" H 3668 5196 50 0000 L CNN
F 1 "10u" H 3668 5105 50 0000 L CNN
F 2 "Capacitor_SMD:C_1206_3216Metric" H 3588 5000 50 0001 C CNN
F 3 "~" H 3550 5150 50 0001 C CNN
1 3550 5150
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR07
U 1 1 5CF715DB
P 3550 4900
F 0 "#PWR07" H 3550 4750 50 0001 C CNN
F 1 "VCC" H 3567 5073 50 0000 C CNN
F 2 "" H 3550 4900 50 0001 C CNN
F 3 "" H 3550 4900 50 0001 C CNN
1 3550 4900
1 0 0 -1
$EndComp
Wire Wire Line
3550 5000 3550 4900
$Comp
L Device:LED D?
U 1 1 5CFB92E6
P 4150 5200
AR Path="/5D77FDBE/5D7AF013/5CFB92E6" Ref="D?" Part="1"
AR Path="/5D77FDBE/5CFB92E6" Ref="D?" Part="1"
AR Path="/5CFB92E6" Ref="D1" Part="1"
F 0 "D1" V 4200 5100 50 0000 R CNN
F 1 "PWR" V 4100 5100 50 0000 R CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 4150 5200 50 0001 C CNN
F 3 "~" H 4150 5200 50 0001 C CNN
1 4150 5200
0 -1 -1 0
$EndComp
$Comp
L Device:R R?
U 1 1 5CFB92EC
P 3950 5000
AR Path="/5D77FDBE/5D7AF013/5CFB92EC" Ref="R?" Part="1"
AR Path="/5D77FDBE/5CFB92EC" Ref="R?" Part="1"
AR Path="/5CFB92EC" Ref="R1" Part="1"
F 0 "R1" H 4020 5046 50 0000 L CNN
F 1 "470" H 4020 4955 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 3880 5000 50 0001 C CNN
F 3 "~" H 3950 5000 50 0001 C CNN
1 3950 5000
0 -1 -1 0
$EndComp
$Comp
L power:VCC #PWR08
U 1 1 5CFBED78
P 3750 4900
F 0 "#PWR08" H 3750 4750 50 0001 C CNN
F 1 "VCC" H 3767 5073 50 0000 C CNN
F 2 "" H 3750 4900 50 0001 C CNN
F 3 "" H 3750 4900 50 0001 C CNN
1 3750 4900
1 0 0 -1
$EndComp
Wire Wire Line
3800 5000 3750 5000
Wire Wire Line
3750 5000 3750 4900
Wire Wire Line
4100 5000 4150 5000
Wire Wire Line
4150 5000 4150 5050
Wire Wire Line
3550 5400 3550 5300
$Comp
L power:GNDD #PWR010
U 1 1 5CF71B50
P 3550 5400
F 0 "#PWR010" H 3550 5150 50 0001 C CNN
F 1 "GNDD" V 3554 5290 50 0000 R CNN
F 2 "" H 3550 5400 50 0001 C CNN
F 3 "" H 3550 5400 50 0001 C CNN
1 3550 5400
1 0 0 -1
$EndComp
Wire Wire Line
4150 5350 4150 5400
$Comp
L power:GNDD #PWR011
U 1 1 5CFBCC03
P 4150 5400
F 0 "#PWR011" H 4150 5150 50 0001 C CNN
F 1 "GNDD" V 4154 5290 50 0000 R CNN
F 2 "" H 4150 5400 50 0001 C CNN
F 3 "" H 4150 5400 50 0001 C CNN
1 4150 5400
1 0 0 -1
$EndComp
Wire Bus Line
7450 4250 7450 4550
Wire Bus Line

3
kicad_pcb/fp-lib-table Normal file
View File

@ -0,0 +1,3 @@
(fp_lib_table
(lib (name lib_mokmod)(type KiCad)(uri ${KIPRJMOD})(options "")(descr ""))
)

View File

@ -0,0 +1,358 @@
(module LOGO (layer F.Cu)
(at 0 0)
(fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.3)))
)
(fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
(effects (font (thickness 0.3)))
)
(fp_poly (pts (xy 3.335488 0.217118) (xy 3.390515 0.219364) (xy 3.392954 0.558031) (xy 3.393295 0.648329) (xy 3.393115 0.747088) (xy 3.392455 0.852171) (xy 3.391353 0.961441) (xy 3.389851 1.072763)
(xy 3.387987 1.183999) (xy 3.385802 1.293014) (xy 3.383335 1.397671) (xy 3.380626 1.495833) (xy 3.377716 1.585366) (xy 3.374643 1.664131) (xy 3.371449 1.729993) (xy 3.370910 1.739516)
(xy 3.365600 1.832800) (xy 3.361066 1.916615) (xy 3.357193 1.993969) (xy 3.353864 2.067865) (xy 3.350963 2.141308) (xy 3.348373 2.217305) (xy 3.345978 2.298861) (xy 3.343662 2.388980)
(xy 3.341308 2.490669) (xy 3.340645 2.520758) (xy 3.337407 2.667333) (xy 3.334396 2.799432) (xy 3.331568 2.917968) (xy 3.328883 3.023856) (xy 3.326295 3.118012) (xy 3.323764 3.201348)
(xy 3.321245 3.274781) (xy 3.318696 3.339224) (xy 3.316074 3.395593) (xy 3.313336 3.444801) (xy 3.310440 3.487764) (xy 3.307342 3.525396) (xy 3.304000 3.558611) (xy 3.300371 3.588325)
(xy 3.296412 3.615452) (xy 3.292080 3.640906) (xy 3.287333 3.665602) (xy 3.286927 3.667607) (xy 3.269294 3.739103) (xy 3.247683 3.797251) (xy 3.221002 3.843823) (xy 3.188165 3.880592)
(xy 3.148081 3.909328) (xy 3.133589 3.917095) (xy 3.103233 3.931578) (xy 3.076144 3.942386) (xy 3.048256 3.950597) (xy 3.015506 3.957290) (xy 2.973827 3.963543) (xy 2.944091 3.967378)
(xy 2.864868 3.976185) (xy 2.770725 3.984739) (xy 2.662136 3.993022) (xy 2.539573 4.001017) (xy 2.403509 4.008706) (xy 2.254417 4.016072) (xy 2.092769 4.023098) (xy 1.919037 4.029766)
(xy 1.733696 4.036058) (xy 1.537217 4.041957) (xy 1.330074 4.047446) (xy 1.112739 4.052507) (xy 0.885684 4.057123) (xy 0.649383 4.061277) (xy 0.404308 4.064950) (xy 0.242454 4.067049)
(xy -0.050031 4.070616) (xy -0.079057 4.033178) (xy -0.102957 3.997871) (xy -0.119384 3.961519) (xy -0.129819 3.919630) (xy -0.135744 3.867710) (xy -0.136281 3.859662) (xy -0.136377 3.853671)
(xy -0.023091 3.853671) (xy -0.023091 3.940849) (xy 0.459894 3.940755) (xy 0.556114 3.940602) (xy 0.656695 3.940197) (xy 0.759020 3.939566) (xy 0.860475 3.938733) (xy 0.958444 3.937726)
(xy 1.050312 3.936569) (xy 1.133464 3.935288) (xy 1.205285 3.933909) (xy 1.239212 3.933112) (xy 1.408900 3.928490) (xy 1.574765 3.923380) (xy 1.735815 3.917835) (xy 1.891054 3.911902)
(xy 2.039491 3.905634) (xy 2.180130 3.899081) (xy 2.311980 3.892292) (xy 2.434046 3.885317) (xy 2.545335 3.878208) (xy 2.644853 3.871014) (xy 2.731608 3.863785) (xy 2.804605 3.856573)
(xy 2.844030 3.851939) (xy 2.921040 3.840802) (xy 2.984293 3.828349) (xy 3.035421 3.813761) (xy 3.076053 3.796223) (xy 3.107820 3.774919) (xy 3.132351 3.749031) (xy 3.151275 3.717744)
(xy 3.161858 3.692742) (xy 3.174572 3.650444) (xy 3.186498 3.595304) (xy 3.197187 3.529868) (xy 3.206191 3.456685) (xy 3.209550 3.422158) (xy 3.212692 3.379905) (xy 3.215815 3.324442)
(xy 3.218858 3.257952) (xy 3.221757 3.182619) (xy 3.224447 3.100626) (xy 3.226865 3.014158) (xy 3.228948 2.925398) (xy 3.230632 2.836530) (xy 3.231854 2.749736) (xy 3.232548 2.667201)
(xy 3.232678 2.628516) (xy 3.233403 2.525290) (xy 3.235212 2.418893) (xy 3.237996 2.312509) (xy 3.241645 2.209325) (xy 3.246048 2.112525) (xy 3.251097 2.025296) (xy 3.255674 1.962728)
(xy 3.258430 1.925334) (xy 3.261549 1.876577) (xy 3.264798 1.820473) (xy 3.267949 1.761042) (xy 3.270771 1.702301) (xy 3.271342 1.689485) (xy 3.272581 1.656172) (xy 3.273915 1.611293)
(xy 3.275323 1.556188) (xy 3.276786 1.492193) (xy 3.278285 1.420648) (xy 3.279800 1.342889) (xy 3.281310 1.260256) (xy 3.282798 1.174086) (xy 3.284243 1.085716) (xy 3.285626 0.996486)
(xy 3.286927 0.907733) (xy 3.288127 0.820795) (xy 3.289205 0.737010) (xy 3.290144 0.657716) (xy 3.290923 0.584251) (xy 3.291522 0.517954) (xy 3.291922 0.460162) (xy 3.292104 0.412213)
(xy 3.292048 0.375445) (xy 3.291734 0.351197) (xy 3.291143 0.340806) (xy 3.291032 0.340528) (xy 3.282782 0.341040) (xy 3.261849 0.344516) (xy 3.230547 0.350458) (xy 3.191193 0.358366)
(xy 3.146102 0.367741) (xy 3.097590 0.378085) (xy 3.047973 0.388898) (xy 2.999566 0.399681) (xy 2.954684 0.409936) (xy 2.915644 0.419164) (xy 2.884761 0.426865) (xy 2.865165 0.432289)
(xy 2.832375 0.444851) (xy 2.811197 0.458432) (xy 2.806422 0.464062) (xy 2.800926 0.480942) (xy 2.796235 0.512067) (xy 2.792498 0.556303) (xy 2.791029 0.583056) (xy 2.786885 0.645974)
(xy 2.780020 0.720476) (xy 2.770903 0.803085) (xy 2.760003 0.890325) (xy 2.747790 0.978718) (xy 2.734731 1.064789) (xy 2.721296 1.145061) (xy 2.707953 1.216057) (xy 2.701481 1.246910)
(xy 2.690900 1.303583) (xy 2.680718 1.374845) (xy 2.670990 1.459894) (xy 2.661769 1.557929) (xy 2.653111 1.668148) (xy 2.645069 1.789750) (xy 2.637696 1.921934) (xy 2.631048 2.063898)
(xy 2.625178 2.214840) (xy 2.620140 2.373960) (xy 2.616863 2.501516) (xy 2.614307 2.605502) (xy 2.611774 2.695077) (xy 2.609206 2.771223) (xy 2.606544 2.834923) (xy 2.603730 2.887159)
(xy 2.600706 2.928913) (xy 2.597413 2.961169) (xy 2.593794 2.984908) (xy 2.589789 3.001113) (xy 2.586769 3.008418) (xy 2.581178 3.014976) (xy 2.570957 3.020772) (xy 2.554674 3.026039)
(xy 2.530895 3.031007) (xy 2.498186 3.035909) (xy 2.455114 3.040977) (xy 2.400245 3.046441) (xy 2.332146 3.052535) (xy 2.293697 3.055805) (xy 2.190547 3.064761) (xy 2.081487 3.074810)
(xy 1.964788 3.086126) (xy 1.838724 3.098882) (xy 1.701567 3.113249) (xy 1.551591 3.129400) (xy 1.485515 3.136631) (xy 1.309180 3.155636) (xy 1.146197 3.172398) (xy 0.994709 3.187074)
(xy 0.852862 3.199823) (xy 0.718801 3.210802) (xy 0.590671 3.220168) (xy 0.466617 3.228078) (xy 0.344785 3.234692) (xy 0.312626 3.236247) (xy 0.254556 3.239179) (xy 0.201459 3.242229)
(xy 0.155285 3.245258) (xy 0.117986 3.248123) (xy 0.091511 3.250683) (xy 0.077812 3.252796) (xy 0.076420 3.253380) (xy 0.070197 3.265417) (xy 0.061741 3.289836) (xy 0.051771 3.323910)
(xy 0.041005 3.364913) (xy 0.030163 3.410118) (xy 0.019963 3.456800) (xy 0.011845 3.498273) (xy -0.010747 3.648450) (xy -0.021827 3.789742) (xy -0.023091 3.853671) (xy -0.136377 3.853671)
(xy -0.137262 3.798995) (xy -0.133829 3.726984) (xy -0.126500 3.646868) (xy -0.115793 3.561885) (xy -0.102228 3.475275) (xy -0.086322 3.390274) (xy -0.068594 3.310123) (xy -0.049562 3.238060)
(xy -0.029744 3.177323) (xy -0.025162 3.165379) (xy -0.006060 3.117273) (xy 0.118197 3.117167) (xy 0.203059 3.116251) (xy 0.296362 3.113608) (xy 0.398755 3.109188) (xy 0.510888 3.102942)
(xy 0.633408 3.094818) (xy 0.766963 3.084768) (xy 0.912203 3.072741) (xy 1.069776 3.058686) (xy 1.240331 3.042555) (xy 1.424516 3.024297) (xy 1.622979 3.003862) (xy 1.720272 2.993608)
(xy 1.847547 2.980052) (xy 1.960346 2.967910) (xy 2.059510 2.957073) (xy 2.145881 2.947428) (xy 2.220301 2.938864) (xy 2.283612 2.931270) (xy 2.336655 2.924534) (xy 2.380273 2.918545)
(xy 2.415306 2.913191) (xy 2.442598 2.908362) (xy 2.462989 2.903946) (xy 2.477321 2.899831) (xy 2.486436 2.895906) (xy 2.491176 2.892060) (xy 2.491517 2.891558) (xy 2.493116 2.881411)
(xy 2.494303 2.858504) (xy 2.495017 2.825467) (xy 2.495198 2.784930) (xy 2.494857 2.744199) (xy 2.494843 2.702989) (xy 2.495702 2.649359) (xy 2.497337 2.586252) (xy 2.499655 2.516612)
(xy 2.502560 2.443381) (xy 2.505956 2.369504) (xy 2.508694 2.316788) (xy 2.512744 2.241659) (xy 2.516885 2.162727) (xy 2.520946 2.083412) (xy 2.524756 2.007134) (xy 2.528142 1.937313)
(xy 2.530933 1.877368) (xy 2.532264 1.847273) (xy 2.535772 1.775526) (xy 2.540105 1.707070) (xy 2.545535 1.639497) (xy 2.552333 1.570400) (xy 2.560769 1.497373) (xy 2.571114 1.418009)
(xy 2.583641 1.329901) (xy 2.598620 1.230643) (xy 2.609773 1.159169) (xy 2.628672 1.036312) (xy 2.644348 0.927828) (xy 2.656878 0.833054) (xy 2.666338 0.751324) (xy 2.672803 0.681977)
(xy 2.676348 0.624347) (xy 2.677051 0.577771) (xy 2.676892 0.570874) (xy 2.674697 0.496455) (xy 2.615292 0.492607) (xy 2.576638 0.488468) (xy 2.552133 0.481858) (xy 2.543402 0.476245)
(xy 2.535673 0.459324) (xy 2.542678 0.439210) (xy 2.564168 0.416233) (xy 2.599891 0.390725) (xy 2.615216 0.381545) (xy 2.645462 0.363063) (xy 2.673297 0.344254) (xy 2.693867 0.328447)
(xy 2.697829 0.324854) (xy 2.721726 0.303894) (xy 2.743334 0.291842) (xy 2.767936 0.287024) (xy 2.800818 0.287766) (xy 2.811932 0.288715) (xy 2.843346 0.290414) (xy 2.877766 0.289642)
(xy 2.917289 0.286122) (xy 2.964008 0.279574) (xy 3.020019 0.269723) (xy 3.087417 0.256290) (xy 3.138746 0.245416) (xy 3.197558 0.233206) (xy 3.244229 0.224674) (xy 3.281464 0.219431)
(xy 3.311970 0.217088) (xy 3.335488 0.217118) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy -2.916316 0.389198) (xy -2.871207 0.389542) (xy -2.836353 0.390237) (xy -2.810042 0.391368) (xy -2.790561 0.393024) (xy -2.776196 0.395292) (xy -2.765237 0.398258) (xy -2.755968 0.402010)
(xy -2.751667 0.404091) (xy -2.719565 0.428723) (xy -2.701637 0.454122) (xy -2.693933 0.468998) (xy -2.688612 0.483233) (xy -2.685240 0.500057) (xy -2.683381 0.522700) (xy -2.682601 0.554393)
(xy -2.682463 0.596516) (xy -2.682701 0.637330) (xy -2.683746 0.669901) (xy -2.686180 0.698332) (xy -2.690587 0.726724) (xy -2.697552 0.759179) (xy -2.707656 0.799801) (xy -2.715856 0.831273)
(xy -2.729640 0.884948) (xy -2.741600 0.934686) (xy -2.751849 0.981994) (xy -2.760496 1.028379) (xy -2.767653 1.075347) (xy -2.773430 1.124404) (xy -2.777939 1.177058) (xy -2.781289 1.234815)
(xy -2.783593 1.299182) (xy -2.784960 1.371664) (xy -2.785502 1.453770) (xy -2.785330 1.547005) (xy -2.784554 1.652876) (xy -2.783535 1.751061) (xy -2.781893 1.884865) (xy -2.780033 2.015487)
(xy -2.777983 2.141822) (xy -2.775769 2.262765) (xy -2.773420 2.377211) (xy -2.770961 2.484056) (xy -2.768420 2.582195) (xy -2.765823 2.670523) (xy -2.763199 2.747936) (xy -2.760573 2.813329)
(xy -2.757973 2.865596) (xy -2.755426 2.903634) (xy -2.755291 2.905251) (xy -2.750248 2.953772) (xy -2.744076 2.988980) (xy -2.736076 3.012954) (xy -2.725550 3.027767) (xy -2.711801 3.035498)
(xy -2.711463 3.035602) (xy -2.700284 3.037310) (xy -2.675473 3.040029) (xy -2.638751 3.043614) (xy -2.591836 3.047919) (xy -2.536447 3.052799) (xy -2.474304 3.058109) (xy -2.407127 3.063704)
(xy -2.336633 3.069438) (xy -2.264543 3.075166) (xy -2.192576 3.080742) (xy -2.122451 3.086022) (xy -2.066637 3.090093) (xy -1.939099 3.098733) (xy -1.822129 3.105498) (xy -1.711039 3.110558)
(xy -1.601137 3.114080) (xy -1.487737 3.116234) (xy -1.366146 3.117189) (xy -1.312323 3.117273) (xy -1.194797 3.116739) (xy -1.091404 3.115060) (xy -1.000917 3.112123) (xy -0.922110 3.107815)
(xy -0.853756 3.102023) (xy -0.794628 3.094632) (xy -0.743499 3.085530) (xy -0.699144 3.074603) (xy -0.660335 3.061738) (xy -0.645032 3.055576) (xy -0.611091 3.041894) (xy -0.587212 3.034962)
(xy -0.569698 3.034625) (xy -0.554853 3.040729) (xy -0.541142 3.051236) (xy -0.519546 3.069865) (xy -0.520350 3.230190) (xy -0.521900 3.315195) (xy -0.525559 3.401413) (xy -0.531099 3.486914)
(xy -0.538294 3.569770) (xy -0.546915 3.648050) (xy -0.556736 3.719825) (xy -0.567529 3.783165) (xy -0.579068 3.836140) (xy -0.591125 3.876820) (xy -0.598584 3.894667) (xy -0.612756 3.920162)
(xy -0.626179 3.935344) (xy -0.643004 3.944496) (xy -0.648882 3.946558) (xy -0.670703 3.951072) (xy -0.705819 3.955125) (xy -0.752138 3.958657) (xy -0.807566 3.961608) (xy -0.870010 3.963921)
(xy -0.937377 3.965535) (xy -1.007574 3.966392) (xy -1.078508 3.966433) (xy -1.148086 3.965599) (xy -1.214214 3.963830) (xy -1.234007 3.963070) (xy -1.334163 3.959979) (xy -1.438101 3.958986)
(xy -1.549619 3.960094) (xy -1.672518 3.963303) (xy -1.674883 3.963381) (xy -1.757755 3.965822) (xy -1.841349 3.967730) (xy -1.923526 3.969094) (xy -2.002144 3.969903) (xy -2.075064 3.970147)
(xy -2.140146 3.969815) (xy -2.195249 3.968896) (xy -2.238233 3.967378) (xy -2.255212 3.966339) (xy -2.323738 3.960698) (xy -2.404951 3.953202) (xy -2.496293 3.944143) (xy -2.595209 3.933809)
(xy -2.699141 3.922490) (xy -2.805532 3.910477) (xy -2.911824 3.898059) (xy -3.015462 3.885527) (xy -3.113889 3.873169) (xy -3.204546 3.861277) (xy -3.284878 3.850140) (xy -3.302000 3.847661)
(xy -3.388908 3.834370) (xy -3.461219 3.821996) (xy -3.519692 3.810367) (xy -3.565084 3.799311) (xy -3.598155 3.788656) (xy -3.619662 3.778230) (xy -3.624814 3.774419) (xy -3.632029 3.767771)
(xy -3.637277 3.760495) (xy -3.640934 3.750138) (xy -3.643371 3.734245) (xy -3.644963 3.710363) (xy -3.646082 3.676038) (xy -3.647103 3.628819) (xy -3.647122 3.627882) (xy -3.647536 3.580823)
(xy -3.647149 3.525487) (xy -3.646059 3.464318) (xy -3.644362 3.399758) (xy -3.642155 3.334250) (xy -3.639536 3.270239) (xy -3.636602 3.210166) (xy -3.633450 3.156475) (xy -3.630178 3.111610)
(xy -3.626881 3.078014) (xy -3.624649 3.062710) (xy -3.615884 3.013818) (xy -3.610156 2.974929) (xy -3.607154 2.941020) (xy -3.606568 2.907067) (xy -3.608086 2.868048) (xy -3.610413 2.832523)
(xy -3.613716 2.793127) (xy -3.618703 2.742536) (xy -3.624932 2.684797) (xy -3.631961 2.623961) (xy -3.639349 2.564077) (xy -3.641465 2.547697) (xy -3.653878 2.442352) (xy -3.662925 2.340388)
(xy -3.668605 2.239325) (xy -3.670307 2.163687) (xy -3.576220 2.163687) (xy -3.575245 2.209535) (xy -3.573013 2.254567) (xy -3.569545 2.300394) (xy -3.564861 2.348628) (xy -3.558981 2.400882)
(xy -3.551928 2.458768) (xy -3.548012 2.489970) (xy -3.533957 2.604232) (xy -3.522429 2.705442) (xy -3.513403 2.795730) (xy -3.506852 2.877225) (xy -3.502751 2.952056) (xy -3.501074 3.022352)
(xy -3.501795 3.090243) (xy -3.504889 3.157858) (xy -3.510329 3.227326) (xy -3.518091 3.300776) (xy -3.528147 3.380338) (xy -3.536501 3.440546) (xy -3.541670 3.483831) (xy -3.545673 3.530686)
(xy -3.547902 3.573387) (xy -3.548162 3.588413) (xy -3.547803 3.621725) (xy -3.546036 3.643464) (xy -3.542085 3.657437) (xy -3.535173 3.667453) (xy -3.531235 3.671363) (xy -3.511691 3.684382)
(xy -3.481106 3.696983) (xy -3.438793 3.709313) (xy -3.384069 3.721519) (xy -3.316250 3.733747) (xy -3.234651 3.746144) (xy -3.138587 3.758857) (xy -3.101879 3.763353) (xy -3.074383 3.766506)
(xy -3.033494 3.770982) (xy -2.981140 3.776584) (xy -2.919248 3.783115) (xy -2.849743 3.790376) (xy -2.774553 3.798172) (xy -2.695603 3.806304) (xy -2.614822 3.814574) (xy -2.534134 3.822785)
(xy -2.455468 3.830741) (xy -2.380749 3.838242) (xy -2.311904 3.845092) (xy -2.250860 3.851094) (xy -2.199543 3.856049) (xy -2.174394 3.858422) (xy -2.124641 3.861393) (xy -2.062120 3.862415)
(xy -1.989327 3.861545) (xy -1.908756 3.858840) (xy -1.822903 3.854355) (xy -1.739515 3.848560) (xy -1.621961 3.840771) (xy -1.507906 3.835889) (xy -1.399730 3.833928) (xy -1.299814 3.834905)
(xy -1.210537 3.838835) (xy -1.143000 3.844710) (xy -1.073220 3.851742) (xy -1.016469 3.855402) (xy -0.970749 3.855652) (xy -0.934062 3.852453) (xy -0.904407 3.845766) (xy -0.888632 3.839833)
(xy -0.868947 3.832036) (xy -0.850522 3.827701) (xy -0.828601 3.826344) (xy -0.798423 3.827482) (xy -0.779676 3.828768) (xy -0.707681 3.834053) (xy -0.693208 3.800860) (xy -0.685397 3.778127)
(xy -0.676896 3.745761) (xy -0.669120 3.709378) (xy -0.666447 3.694474) (xy -0.660075 3.652653) (xy -0.653762 3.604184) (xy -0.647672 3.551149) (xy -0.641969 3.495626) (xy -0.636817 3.439696)
(xy -0.632380 3.385437) (xy -0.628821 3.334930) (xy -0.626305 3.290254) (xy -0.624996 3.253489) (xy -0.625058 3.226714) (xy -0.626654 3.212010) (xy -0.628239 3.209820) (xy -0.639468 3.211627)
(xy -0.659154 3.215904) (xy -0.665788 3.217483) (xy -0.709546 3.225893) (xy -0.766667 3.233384) (xy -0.835143 3.239882) (xy -0.912964 3.245313) (xy -0.998124 3.249603) (xy -1.088615 3.252679)
(xy -1.182427 3.254467) (xy -1.277553 3.254892) (xy -1.371985 3.253881) (xy -1.463715 3.251360) (xy -1.520152 3.248916) (xy -1.580007 3.245570) (xy -1.650306 3.241085) (xy -1.726171 3.235805)
(xy -1.802725 3.230078) (xy -1.875089 3.224248) (xy -1.908849 3.221344) (xy -1.999620 3.213363) (xy -2.078451 3.206516) (xy -2.148729 3.200528) (xy -2.213844 3.195125) (xy -2.277182 3.190031)
(xy -2.342134 3.184971) (xy -2.412086 3.179670) (xy -2.490428 3.173853) (xy -2.528455 3.171058) (xy -2.617099 3.164305) (xy -2.691193 3.158092) (xy -2.751569 3.152327) (xy -2.799057 3.146913)
(xy -2.834489 3.141758) (xy -2.858694 3.136766) (xy -2.872222 3.131997) (xy -2.877937 3.126561) (xy -2.882356 3.116139) (xy -2.885536 3.099312) (xy -2.887534 3.074662) (xy -2.888410 3.040770)
(xy -2.888221 2.996218) (xy -2.887025 2.939586) (xy -2.884881 2.869455) (xy -2.884007 2.844031) (xy -2.881891 2.761442) (xy -2.880805 2.667108) (xy -2.880702 2.564640) (xy -2.881536 2.457648)
(xy -2.883260 2.349743) (xy -2.885827 2.244536) (xy -2.889190 2.145639) (xy -2.893303 2.056661) (xy -2.894474 2.035849) (xy -2.896964 1.979357) (xy -2.898667 1.910223) (xy -2.899610 1.831178)
(xy -2.899820 1.744952) (xy -2.899324 1.654275) (xy -2.898149 1.561878) (xy -2.896322 1.470492) (xy -2.893870 1.382846) (xy -2.890820 1.301672) (xy -2.887199 1.229700) (xy -2.886376 1.216122)
(xy -2.879780 1.124644) (xy -2.871921 1.044189) (xy -2.862159 0.970396) (xy -2.849856 0.898906) (xy -2.834373 0.825361) (xy -2.820778 0.768201) (xy -2.809240 0.719778) (xy -2.798778 0.672626)
(xy -2.790122 0.630297) (xy -2.784007 0.596345) (xy -2.781377 0.576995) (xy -2.779228 0.549386) (xy -2.779921 0.532467) (xy -2.784548 0.521631) (xy -2.794203 0.512274) (xy -2.797335 0.509780)
(xy -2.825868 0.494830) (xy -2.867943 0.483557) (xy -2.922119 0.476103) (xy -2.986956 0.472611) (xy -3.061013 0.473223) (xy -3.128818 0.476977) (xy -3.161311 0.479818) (xy -3.201578 0.483966)
(xy -3.247141 0.489098) (xy -3.295522 0.494892) (xy -3.344242 0.501028) (xy -3.390824 0.507181) (xy -3.432787 0.513032) (xy -3.467655 0.518257) (xy -3.492949 0.522534) (xy -3.506190 0.525542)
(xy -3.507461 0.526168) (xy -3.507602 0.533998) (xy -3.507096 0.555114) (xy -3.506016 0.587426) (xy -3.504437 0.628842) (xy -3.502434 0.677273) (xy -3.500616 0.718754) (xy -3.497926 0.791863)
(xy -3.496558 0.864260) (xy -3.496589 0.937825) (xy -3.498098 1.014439) (xy -3.501163 1.095982) (xy -3.505863 1.184334) (xy -3.512275 1.281375) (xy -3.520480 1.388985) (xy -3.530554 1.509044)
(xy -3.536290 1.574031) (xy -3.546114 1.684452) (xy -3.554516 1.781159) (xy -3.561517 1.865764) (xy -3.567136 1.939880) (xy -3.571396 2.005117) (xy -3.574316 2.063090) (xy -3.575917 2.115409)
(xy -3.576220 2.163687) (xy -3.670307 2.163687) (xy -3.670915 2.136682) (xy -3.669853 2.029978) (xy -3.665418 1.916732) (xy -3.657609 1.794463) (xy -3.646422 1.660691) (xy -3.640764 1.600970)
(xy -3.631232 1.493852) (xy -3.623625 1.386507) (xy -3.617850 1.276375) (xy -3.613815 1.160896) (xy -3.611430 1.037509) (xy -3.610602 0.903653) (xy -3.611113 0.772243) (xy -3.613728 0.439971)
(xy -3.544455 0.427237) (xy -3.488926 0.417269) (xy -3.440151 0.409218) (xy -3.395427 0.402877) (xy -3.352051 0.398041) (xy -3.307321 0.394504) (xy -3.258535 0.392063) (xy -3.202991 0.390510)
(xy -3.137985 0.389641) (xy -3.060815 0.389250) (xy -3.044152 0.389212) (xy -2.973394 0.389117) (xy -2.916316 0.389198) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy 0.405022 0.289728) (xy 0.426331 0.302757) (xy 0.442329 0.325387) (xy 0.442948 0.326826) (xy 0.453825 0.371438) (xy 0.453078 0.425524) (xy 0.440683 0.489232) (xy 0.416617 0.562710)
(xy 0.398737 0.606556) (xy 0.381322 0.649856) (xy 0.370442 0.686670) (xy 0.366165 0.720695) (xy 0.368562 0.755627) (xy 0.377700 0.795161) (xy 0.393649 0.842994) (xy 0.403657 0.869758)
(xy 0.428101 0.936650) (xy 0.446891 0.995877) (xy 0.460810 1.051555) (xy 0.470640 1.107799) (xy 0.477163 1.168725) (xy 0.481161 1.238447) (xy 0.482652 1.285394) (xy 0.483872 1.342849)
(xy 0.484175 1.388485) (xy 0.483389 1.425860) (xy 0.481344 1.458532) (xy 0.477866 1.490059) (xy 0.472783 1.523999) (xy 0.470427 1.538078) (xy 0.450349 1.634125) (xy 0.423959 1.719609)
(xy 0.389670 1.797508) (xy 0.345894 1.870804) (xy 0.291045 1.942478) (xy 0.223535 2.015510) (xy 0.207905 2.031001) (xy 0.144998 2.087636) (xy 0.085307 2.130837) (xy 0.026981 2.161703)
(xy -0.031832 2.181336) (xy -0.052366 2.185666) (xy -0.092531 2.188922) (xy -0.143665 2.186880) (xy -0.202499 2.180093) (xy -0.265765 2.169115) (xy -0.330194 2.154500) (xy -0.392517 2.136804)
(xy -0.441681 2.119643) (xy -0.479270 2.105122) (xy -0.497313 2.128213) (xy -0.508811 2.143247) (xy -0.527009 2.167406) (xy -0.549462 2.197433) (xy -0.573727 2.230069) (xy -0.575178 2.232026)
(xy -0.612160 2.279092) (xy -0.644501 2.314403) (xy -0.671533 2.337321) (xy -0.692589 2.347211) (xy -0.696521 2.347576) (xy -0.708404 2.342349) (xy -0.718474 2.333500) (xy -0.729843 2.310696)
(xy -0.728967 2.280642) (xy -0.715724 2.243029) (xy -0.689991 2.197547) (xy -0.651648 2.143884) (xy -0.636235 2.124364) (xy -0.609027 2.089661) (xy -0.590577 2.061895) (xy -0.580458 2.037460)
(xy -0.578245 2.012749) (xy -0.580884 1.998411) (xy -0.404755 1.998411) (xy -0.394858 2.005788) (xy -0.381169 2.004416) (xy -0.366335 2.003301) (xy -0.361758 2.007525) (xy -0.355230 2.021755)
(xy -0.339761 2.034082) (xy -0.321526 2.039681) (xy -0.320589 2.039697) (xy -0.304732 2.045233) (xy -0.286973 2.058929) (xy -0.283348 2.062788) (xy -0.271270 2.075138) (xy -0.259118 2.082056)
(xy -0.242008 2.085081) (xy -0.215054 2.085752) (xy -0.210437 2.085746) (xy -0.172697 2.083848) (xy -0.131434 2.079106) (xy -0.106650 2.074773) (xy -0.060339 2.062315) (xy -0.018982 2.044653)
(xy 0.022335 2.019289) (xy 0.062131 1.988963) (xy 0.115325 1.940430) (xy 0.169541 1.881462) (xy 0.221273 1.816335) (xy 0.267013 1.749327) (xy 0.288407 1.713106) (xy 0.321114 1.642400)
(xy 0.345508 1.562701) (xy 0.361835 1.472784) (xy 0.370340 1.371420) (xy 0.371787 1.296940) (xy 0.370494 1.228430) (xy 0.366548 1.171325) (xy 0.359233 1.121758) (xy 0.347836 1.075863)
(xy 0.331641 1.029773) (xy 0.315336 0.991460) (xy 0.300626 0.957305) (xy 0.287449 0.924070) (xy 0.277886 0.897106) (xy 0.275415 0.888813) (xy 0.268875 0.868436) (xy 0.262808 0.856075)
(xy 0.260616 0.854364) (xy 0.250096 0.860982) (xy 0.233137 0.880073) (xy 0.210480 0.910495) (xy 0.182863 0.951101) (xy 0.151028 1.000751) (xy 0.115715 1.058298) (xy 0.077664 1.122600)
(xy 0.037616 1.192513) (xy 0.011533 1.239213) (xy -0.016141 1.288597) (xy -0.044803 1.338605) (xy -0.072459 1.385835) (xy -0.097113 1.426889) (xy -0.116771 1.458366) (xy -0.119410 1.462425)
(xy -0.144649 1.502196) (xy -0.172687 1.548554) (xy -0.202605 1.599769) (xy -0.233482 1.654115) (xy -0.264400 1.709865) (xy -0.294439 1.765292) (xy -0.322680 1.818668) (xy -0.348202 1.868266)
(xy -0.370087 1.912358) (xy -0.387414 1.949219) (xy -0.399265 1.977120) (xy -0.404720 1.994333) (xy -0.404755 1.998411) (xy -0.580884 1.998411) (xy -0.583509 1.984155) (xy -0.595825 1.948072)
(xy -0.610910 1.910310) (xy -0.633254 1.852324) (xy -0.649760 1.800391) (xy -0.661374 1.749853) (xy -0.669041 1.696051) (xy -0.673706 1.634329) (xy -0.675430 1.592389) (xy -0.674930 1.523462)
(xy -0.561102 1.523462) (xy -0.560031 1.601195) (xy -0.556367 1.667559) (xy -0.549928 1.724483) (xy -0.540530 1.773898) (xy -0.527993 1.817734) (xy -0.521838 1.834712) (xy -0.513681 1.856559)
(xy -0.507228 1.872717) (xy -0.501307 1.882241) (xy -0.494746 1.884182) (xy -0.486375 1.877593) (xy -0.475020 1.861528) (xy -0.459511 1.835038) (xy -0.438674 1.797178) (xy -0.411339 1.746999)
(xy -0.409773 1.744136) (xy -0.387314 1.702292) (xy -0.366313 1.661717) (xy -0.348445 1.625750) (xy -0.335385 1.597734) (xy -0.330342 1.585576) (xy -0.319274 1.561222) (xy -0.301976 1.529091)
(xy -0.281120 1.493967) (xy -0.265811 1.470122) (xy -0.245755 1.438659) (xy -0.220850 1.397532) (xy -0.193419 1.350696) (xy -0.165788 1.302108) (xy -0.145926 1.266152) (xy -0.104665 1.190687)
(xy -0.068822 1.126077) (xy -0.036737 1.069507) (xy -0.006749 1.018162) (xy 0.022802 0.969227) (xy 0.053576 0.919887) (xy 0.087233 0.867328) (xy 0.109390 0.833247) (xy 0.143389 0.780589)
(xy 0.169248 0.738716) (xy 0.187664 0.705803) (xy 0.199330 0.680029) (xy 0.204940 0.659570) (xy 0.205188 0.642601) (xy 0.200769 0.627301) (xy 0.193184 0.613139) (xy 0.157429 0.568962)
(xy 0.110043 0.531084) (xy 0.054020 0.501011) (xy -0.007643 0.480248) (xy -0.071950 0.470302) (xy -0.092364 0.469650) (xy -0.143915 0.472713) (xy -0.185472 0.482720) (xy -0.221268 0.500725)
(xy -0.223922 0.502483) (xy -0.257142 0.531378) (xy -0.292307 0.573968) (xy -0.328659 0.628792) (xy -0.365441 0.694390) (xy -0.401895 0.769300) (xy -0.437263 0.852064) (xy -0.470788 0.941219)
(xy -0.501711 1.035306) (xy -0.503676 1.041762) (xy -0.520126 1.098749) (xy -0.532918 1.150182) (xy -0.542571 1.199684) (xy -0.549606 1.250875) (xy -0.554543 1.307377) (xy -0.557901 1.372810)
(xy -0.559760 1.432427) (xy -0.561102 1.523462) (xy -0.674930 1.523462) (xy -0.674430 1.454620) (xy -0.662368 1.314522) (xy -0.638940 1.169636) (xy -0.604344 1.019425) (xy -0.566509 0.890230)
(xy -0.524096 0.774432) (xy -0.477254 0.672250) (xy -0.426132 0.583900) (xy -0.370877 0.509599) (xy -0.311638 0.449565) (xy -0.248563 0.404014) (xy -0.181802 0.373163) (xy -0.157519 0.365860)
(xy -0.089611 0.354667) (xy -0.023314 0.357260) (xy 0.042379 0.373942) (xy 0.108475 0.405015) (xy 0.175981 0.450784) (xy 0.205711 0.475073) (xy 0.232506 0.497546) (xy 0.255246 0.515720)
(xy 0.271304 0.527550) (xy 0.277765 0.531091) (xy 0.289314 0.523509) (xy 0.300966 0.501208) (xy 0.312457 0.464863) (xy 0.323522 0.415144) (xy 0.323603 0.414720) (xy 0.330841 0.379063)
(xy 0.338100 0.347034) (xy 0.344359 0.322967) (xy 0.347443 0.313554) (xy 0.361757 0.294595) (xy 0.382224 0.286830) (xy 0.405022 0.289728) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy -1.349578 1.351127) (xy -1.321549 1.352127) (xy -1.301520 1.354600) (xy -1.285794 1.359158) (xy -1.270676 1.366416) (xy -1.260235 1.372394) (xy -1.221215 1.402412) (xy -1.183955 1.445834)
(xy -1.147860 1.503429) (xy -1.126795 1.544525) (xy -1.103044 1.598056) (xy -1.085449 1.648373) (xy -1.072994 1.699871) (xy -1.064666 1.756944) (xy -1.059449 1.823986) (xy -1.058661 1.839576)
(xy -1.057353 1.886067) (xy -1.057292 1.939077) (xy -1.058341 1.995698) (xy -1.060359 2.053021) (xy -1.063210 2.108137) (xy -1.066753 2.158138) (xy -1.070850 2.200115) (xy -1.075361 2.231160)
(xy -1.077889 2.242243) (xy -1.092541 2.275664) (xy -1.113353 2.295005) (xy -1.140252 2.300227) (xy -1.168287 2.293357) (xy -1.185878 2.286295) (xy -1.183681 2.010981) (xy -1.183127 1.938547)
(xy -1.182795 1.879723) (xy -1.182772 1.832727) (xy -1.183144 1.795776) (xy -1.183999 1.767086) (xy -1.185423 1.744876) (xy -1.187502 1.727362) (xy -1.190324 1.712761) (xy -1.193975 1.699290)
(xy -1.198541 1.685168) (xy -1.199680 1.681788) (xy -1.228345 1.608495) (xy -1.259782 1.550072) (xy -1.293920 1.506581) (xy -1.330689 1.478080) (xy -1.370017 1.464628) (xy -1.411836 1.466285)
(xy -1.443960 1.477098) (xy -1.485522 1.503703) (xy -1.525994 1.544843) (xy -1.564931 1.599672) (xy -1.601890 1.667346) (xy -1.636427 1.747018) (xy -1.668099 1.837845) (xy -1.696461 1.938979)
(xy -1.704973 1.974273) (xy -1.720211 2.037053) (xy -1.733878 2.086115) (xy -1.746721 2.122962) (xy -1.759486 2.149095) (xy -1.772919 2.166016) (xy -1.787767 2.175225) (xy -1.804776 2.178226)
(xy -1.806352 2.178243) (xy -1.826869 2.171330) (xy -1.845297 2.153435) (xy -1.857426 2.128822) (xy -1.858246 2.125674) (xy -1.860128 2.111654) (xy -1.862442 2.085078) (xy -1.864991 2.048768)
(xy -1.867575 2.005551) (xy -1.869966 1.958879) (xy -1.874403 1.882734) (xy -1.880098 1.819854) (xy -1.887416 1.768136) (xy -1.896725 1.725479) (xy -1.908391 1.689779) (xy -1.921952 1.660462)
(xy -1.943997 1.627408) (xy -1.967671 1.608808) (xy -1.994656 1.603723) (xy -2.016378 1.607689) (xy -2.038719 1.617028) (xy -2.056044 1.628698) (xy -2.057624 1.630304) (xy -2.071853 1.653249)
(xy -2.085973 1.689428) (xy -2.099514 1.736686) (xy -2.112002 1.792868) (xy -2.122966 1.855817) (xy -2.131936 1.923378) (xy -2.138438 1.993396) (xy -2.139078 2.002580) (xy -2.142112 2.043373)
(xy -2.145368 2.079611) (xy -2.148512 2.108048) (xy -2.151212 2.125439) (xy -2.151954 2.128214) (xy -2.165863 2.152561) (xy -2.185806 2.170577) (xy -2.207071 2.178099) (xy -2.208448 2.178125)
(xy -2.223177 2.177156) (xy -2.234993 2.173431) (xy -2.244215 2.165433) (xy -2.251159 2.151645) (xy -2.256141 2.130550) (xy -2.259479 2.100633) (xy -2.261489 2.060374) (xy -2.262489 2.008259)
(xy -2.262795 1.942769) (xy -2.262798 1.917969) (xy -2.262361 1.842562) (xy -2.261189 1.768124) (xy -2.259367 1.696475) (xy -2.256981 1.629437) (xy -2.254116 1.568831) (xy -2.250856 1.516480)
(xy -2.247287 1.474204) (xy -2.243494 1.443826) (xy -2.239882 1.427955) (xy -2.227147 1.409646) (xy -2.213349 1.399663) (xy -2.190371 1.396337) (xy -2.169942 1.407032) (xy -2.153803 1.430392)
(xy -2.146455 1.451660) (xy -2.138964 1.473453) (xy -2.130182 1.488195) (xy -2.126399 1.491125) (xy -2.113806 1.491456) (xy -2.091067 1.488319) (xy -2.062864 1.482381) (xy -2.059878 1.481648)
(xy -2.007616 1.472683) (xy -1.962890 1.474619) (xy -1.921934 1.487904) (xy -1.898619 1.500861) (xy -1.870021 1.522616) (xy -1.844613 1.550581) (xy -1.820182 1.587659) (xy -1.794512 1.636751)
(xy -1.793831 1.638166) (xy -1.780930 1.663938) (xy -1.770256 1.683277) (xy -1.763680 1.692853) (xy -1.762860 1.693334) (xy -1.758272 1.686661) (xy -1.750121 1.668969) (xy -1.739983 1.643751)
(xy -1.737517 1.637202) (xy -1.713129 1.582844) (xy -1.681293 1.528680) (xy -1.644305 1.477555) (xy -1.604462 1.432315) (xy -1.564058 1.395803) (xy -1.525392 1.370864) (xy -1.520778 1.368694)
(xy -1.501327 1.360914) (xy -1.481740 1.355783) (xy -1.458078 1.352771) (xy -1.426399 1.351347) (xy -1.389303 1.350987) (xy -1.349578 1.351127) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy 1.906292 0.083636) (xy 1.919276 0.100994) (xy 1.931440 0.127954) (xy 1.941464 0.161675) (xy 1.947335 0.193704) (xy 1.951079 0.232268) (xy 1.954125 0.284837) (xy 1.956493 0.350042)
(xy 1.958201 0.426509) (xy 1.959268 0.512870) (xy 1.959714 0.607751) (xy 1.959557 0.709781) (xy 1.958816 0.817590) (xy 1.957510 0.929807) (xy 1.955658 1.045059) (xy 1.953278 1.161976)
(xy 1.950391 1.279187) (xy 1.947015 1.395319) (xy 1.943168 1.509003) (xy 1.938870 1.618866) (xy 1.934139 1.723538) (xy 1.928995 1.821647) (xy 1.923654 1.908849) (xy 1.919604 1.963354)
(xy 1.915341 2.004600) (xy 1.910373 2.034721) (xy 1.904206 2.055848) (xy 1.896349 2.070114) (xy 1.886309 2.079652) (xy 1.883833 2.081281) (xy 1.866423 2.084527) (xy 1.849175 2.074465)
(xy 1.833477 2.053134) (xy 1.820720 2.022572) (xy 1.812293 1.984817) (xy 1.811025 1.974481) (xy 1.806747 1.948600) (xy 1.800815 1.934112) (xy 1.797224 1.931940) (xy 1.787871 1.936542)
(xy 1.769359 1.949073) (xy 1.744368 1.967618) (xy 1.715575 1.990266) (xy 1.715558 1.990280) (xy 1.648131 2.040153) (xy 1.586416 2.076146) (xy 1.529913 2.098461) (xy 1.478121 2.107300)
(xy 1.435485 2.103978) (xy 1.397504 2.095109) (xy 1.370150 2.085630) (xy 1.348754 2.073217) (xy 1.328645 2.055540) (xy 1.319786 2.046337) (xy 1.288896 2.006122) (xy 1.259956 1.955137)
(xy 1.235148 1.898006) (xy 1.216655 1.839352) (xy 1.211647 1.817175) (xy 1.204493 1.764081) (xy 1.201553 1.702369) (xy 1.201614 1.698692) (xy 1.311750 1.698692) (xy 1.314554 1.754465)
(xy 1.321754 1.803943) (xy 1.330186 1.834446) (xy 1.349062 1.875740) (xy 1.373434 1.913842) (xy 1.400993 1.946235) (xy 1.429426 1.970405) (xy 1.456423 1.983839) (xy 1.469255 1.985746)
(xy 1.486596 1.981964) (xy 1.510991 1.972233) (xy 1.531697 1.961646) (xy 1.560108 1.942100) (xy 1.594429 1.913291) (xy 1.631512 1.878403) (xy 1.668207 1.840619) (xy 1.701366 1.803122)
(xy 1.727842 1.769097) (xy 1.738993 1.752039) (xy 1.754299 1.722938) (xy 1.759003 1.702655) (xy 1.752316 1.688145) (xy 1.733443 1.676361) (xy 1.717649 1.669962) (xy 1.692410 1.659617)
(xy 1.678397 1.649348) (xy 1.674092 1.635329) (xy 1.677980 1.613731) (xy 1.685681 1.589289) (xy 1.698064 1.539092) (xy 1.698585 1.495401) (xy 1.686900 1.454507) (xy 1.670350 1.424109)
(xy 1.641984 1.385897) (xy 1.613025 1.360702) (xy 1.580218 1.346375) (xy 1.544242 1.340972) (xy 1.516015 1.340319) (xy 1.495054 1.343617) (xy 1.474071 1.352730) (xy 1.455158 1.363757)
(xy 1.414815 1.396217) (xy 1.378385 1.440821) (xy 1.348095 1.494411) (xy 1.329780 1.541624) (xy 1.319356 1.587469) (xy 1.313348 1.641426) (xy 1.311750 1.698692) (xy 1.201614 1.698692)
(xy 1.202643 1.637130) (xy 1.207580 1.573455) (xy 1.216181 1.516437) (xy 1.223567 1.485641) (xy 1.251286 1.408626) (xy 1.285941 1.345285) (xy 1.327741 1.295448) (xy 1.376894 1.258944)
(xy 1.433610 1.235601) (xy 1.498098 1.225248) (xy 1.541318 1.225237) (xy 1.607528 1.234772) (xy 1.664999 1.255559) (xy 1.712705 1.286988) (xy 1.749622 1.328448) (xy 1.767008 1.359732)
(xy 1.780626 1.387501) (xy 1.790807 1.401316) (xy 1.798783 1.401892) (xy 1.805781 1.389946) (xy 1.808012 1.383602) (xy 1.813078 1.364640) (xy 1.817561 1.340042) (xy 1.821540 1.308610)
(xy 1.825090 1.269149) (xy 1.828288 1.220462) (xy 1.831211 1.161353) (xy 1.833936 1.090627) (xy 1.836540 1.007088) (xy 1.839098 0.909538) (xy 1.839502 0.892849) (xy 1.842712 0.761739)
(xy 1.845745 0.645194) (xy 1.848657 0.542384) (xy 1.851502 0.452482) (xy 1.854336 0.374660) (xy 1.857215 0.308090) (xy 1.860193 0.251944) (xy 1.863325 0.205393) (xy 1.866668 0.167609)
(xy 1.870275 0.137765) (xy 1.874203 0.115032) (xy 1.878507 0.098582) (xy 1.883241 0.087587) (xy 1.888462 0.081219) (xy 1.893813 0.078721) (xy 1.906292 0.083636) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy -0.729889 -3.947481) (xy -0.669195 -3.946669) (xy -0.613521 -3.945692) (xy -0.564712 -3.944600) (xy -0.524608 -3.943444) (xy -0.495054 -3.942275) (xy -0.477891 -3.941143) (xy -0.474272 -3.940473)
(xy -0.471884 -3.931547) (xy -0.468671 -3.910655) (xy -0.465098 -3.881168) (xy -0.462429 -3.855069) (xy -0.457323 -3.807765) (xy -0.450940 -3.762589) (xy -0.442628 -3.716289) (xy -0.431732 -3.665616)
(xy -0.417598 -3.607317) (xy -0.399574 -3.538143) (xy -0.396115 -3.525212) (xy -0.374884 -3.444274) (xy -0.358049 -3.375760) (xy -0.345157 -3.317480) (xy -0.335755 -3.267248) (xy -0.329391 -3.222875)
(xy -0.325856 -3.185721) (xy -0.323939 -3.151808) (xy -0.324473 -3.127764) (xy -0.328203 -3.108159) (xy -0.335868 -3.087562) (xy -0.340771 -3.076587) (xy -0.359651 -3.043821) (xy -0.382860 -3.022648)
(xy -0.414952 -3.009269) (xy -0.424420 -3.006810) (xy -0.435970 -3.005145) (xy -0.461278 -3.002240) (xy -0.498770 -2.998254) (xy -0.546876 -2.993344) (xy -0.604021 -2.987668) (xy -0.668634 -2.981384)
(xy -0.739142 -2.974650) (xy -0.813973 -2.967625) (xy -0.820814 -2.966988) (xy -0.962724 -2.953627) (xy -1.091436 -2.941108) (xy -1.209109 -2.929166) (xy -1.317900 -2.917535) (xy -1.419966 -2.905951)
(xy -1.517465 -2.894148) (xy -1.612553 -2.881860) (xy -1.707388 -2.868823) (xy -1.804128 -2.854771) (xy -1.904929 -2.839438) (xy -2.011949 -2.822560) (xy -2.066637 -2.813754) (xy -2.158036 -2.799365)
(xy -2.243846 -2.786663) (xy -2.322462 -2.775851) (xy -2.392279 -2.767130) (xy -2.451693 -2.760700) (xy -2.499100 -2.756763) (xy -2.531307 -2.755515) (xy -2.563800 -2.753874) (xy -2.587991 -2.749390)
(xy -2.597296 -2.745237) (xy -2.604933 -2.738597) (xy -2.607433 -2.730660) (xy -2.604756 -2.717039) (xy -2.596864 -2.693344) (xy -2.596843 -2.693282) (xy -2.590678 -2.672309) (xy -2.586463 -2.648772)
(xy -2.583879 -2.619319) (xy -2.582612 -2.580597) (xy -2.582334 -2.539504) (xy -2.582334 -2.427403) (xy -2.611794 -2.371165) (xy -2.622072 -2.351248) (xy -2.630917 -2.332765) (xy -2.638454 -2.314412)
(xy -2.644809 -2.294885) (xy -2.650109 -2.272879) (xy -2.654479 -2.247092) (xy -2.658045 -2.216218) (xy -2.660934 -2.178953) (xy -2.663270 -2.133995) (xy -2.665180 -2.080037) (xy -2.666790 -2.015777)
(xy -2.668226 -1.939911) (xy -2.669613 -1.851134) (xy -2.670930 -1.758757) (xy -2.672466 -1.651840) (xy -2.673954 -1.558289) (xy -2.675512 -1.476077) (xy -2.677256 -1.403177) (xy -2.679307 -1.337561)
(xy -2.681781 -1.277202) (xy -2.684797 -1.220073) (xy -2.688473 -1.164148) (xy -2.692928 -1.107398) (xy -2.698278 -1.047797) (xy -2.704643 -0.983318) (xy -2.712140 -0.911933) (xy -2.720887 -0.831615)
(xy -2.729450 -0.754303) (xy -2.739863 -0.657394) (xy -2.747917 -0.574879) (xy -2.753645 -0.505944) (xy -2.757083 -0.449774) (xy -2.758264 -0.405557) (xy -2.757224 -0.372479) (xy -2.753996 -0.349726)
(xy -2.748615 -0.336484) (xy -2.747204 -0.334825) (xy -2.734764 -0.327801) (xy -2.711206 -0.318865) (xy -2.680448 -0.309404) (xy -2.660174 -0.304053) (xy -2.594569 -0.285253) (xy -2.540578 -0.264410)
(xy -2.499053 -0.242022) (xy -2.470844 -0.218589) (xy -2.456804 -0.194610) (xy -2.455334 -0.184043) (xy -2.457074 -0.168605) (xy -2.465481 -0.162632) (xy -2.480349 -0.161820) (xy -2.504996 -0.163837)
(xy -2.532578 -0.168540) (xy -2.536152 -0.169357) (xy -2.555121 -0.172876) (xy -2.585579 -0.177378) (xy -2.623698 -0.182342) (xy -2.665647 -0.187247) (xy -2.676375 -0.188413) (xy -2.734639 -0.195908)
(xy -2.787798 -0.205166) (xy -2.831533 -0.215391) (xy -2.844832 -0.219382) (xy -2.877813 -0.228465) (xy -2.918933 -0.236678) (xy -2.969266 -0.244131) (xy -3.029887 -0.250931) (xy -3.101869 -0.257189)
(xy -3.186287 -0.263014) (xy -3.284216 -0.268515) (xy -3.367424 -0.272505) (xy -3.438297 -0.275531) (xy -3.494936 -0.277550) (xy -3.538468 -0.278569) (xy -3.570020 -0.278596) (xy -3.590718 -0.277639)
(xy -3.601690 -0.275708) (xy -3.603988 -0.274231) (xy -3.608032 -0.261050) (xy -3.610285 -0.240620) (xy -3.610353 -0.238606) (xy -3.614610 -0.203304) (xy -3.624377 -0.171595) (xy -3.637957 -0.148153)
(xy -3.645875 -0.140838) (xy -3.659402 -0.134090) (xy -3.670110 -0.137831) (xy -3.677955 -0.145045) (xy -3.690367 -0.167017) (xy -3.697895 -0.202866) (xy -3.698166 -0.205261) (xy -3.702488 -0.241215)
(xy -3.706868 -0.265446) (xy -3.712480 -0.281585) (xy -3.720496 -0.293263) (xy -3.729332 -0.301750) (xy -3.748316 -0.318257) (xy -3.728742 -0.351656) (xy -3.720499 -0.371109) (xy -3.594485 -0.371109)
(xy -3.461712 -0.366331) (xy -3.412318 -0.364560) (xy -3.352350 -0.362419) (xy -3.286617 -0.360080) (xy -3.219931 -0.357714) (xy -3.157102 -0.355492) (xy -3.148061 -0.355173) (xy -3.095032 -0.353295)
(xy -3.045577 -0.351529) (xy -3.002303 -0.349969) (xy -2.967815 -0.348709) (xy -2.944719 -0.347845) (xy -2.937969 -0.347578) (xy -2.911245 -0.350690) (xy -2.891010 -0.364108) (xy -2.883336 -0.375085)
(xy -2.876152 -0.392914) (xy -2.869199 -0.418961) (xy -2.862216 -0.454596) (xy -2.854943 -0.501184) (xy -2.847119 -0.560093) (xy -2.838483 -0.632690) (xy -2.836475 -0.650393) (xy -2.826198 -0.747135)
(xy -2.816946 -0.846211) (xy -2.808642 -0.949072) (xy -2.801209 -1.057169) (xy -2.794571 -1.171951) (xy -2.788652 -1.294869) (xy -2.783374 -1.427373) (xy -2.778661 -1.570914) (xy -2.774436 -1.726941)
(xy -2.770624 -1.896904) (xy -2.770616 -1.897303) (xy -2.768704 -1.987056) (xy -2.766826 -2.063160) (xy -2.764803 -2.127361) (xy -2.762454 -2.181403) (xy -2.759600 -2.227028) (xy -2.756062 -2.265983)
(xy -2.751658 -2.300011) (xy -2.746211 -2.330856) (xy -2.739540 -2.360262) (xy -2.731466 -2.389975) (xy -2.721808 -2.421738) (xy -2.714121 -2.445782) (xy -2.702962 -2.482429) (xy -2.693938 -2.516118)
(xy -2.688059 -2.542807) (xy -2.686288 -2.557175) (xy -2.688310 -2.574788) (xy -2.693747 -2.602982) (xy -2.701719 -2.637554) (xy -2.709334 -2.667000) (xy -2.724051 -2.728502) (xy -2.731160 -2.776682)
(xy -2.730665 -2.811593) (xy -2.722569 -2.833294) (xy -2.720632 -2.835481) (xy -2.714209 -2.840827) (xy -2.705552 -2.845152) (xy -2.692763 -2.848695) (xy -2.673946 -2.851699) (xy -2.647203 -2.854406)
(xy -2.610636 -2.857057) (xy -2.562349 -2.859894) (xy -2.505364 -2.862906) (xy -2.446731 -2.866190) (xy -2.392889 -2.869881) (xy -2.341168 -2.874293) (xy -2.288901 -2.879740) (xy -2.233419 -2.886536)
(xy -2.172054 -2.894997) (xy -2.102137 -2.905436) (xy -2.021001 -2.918168) (xy -1.978121 -2.925052) (xy -1.848514 -2.945009) (xy -1.706347 -2.965157) (xy -1.554447 -2.985166) (xy -1.395638 -3.004706)
(xy -1.232747 -3.023446) (xy -1.068600 -3.041057) (xy -0.906021 -3.057208) (xy -0.747837 -3.071570) (xy -0.663520 -3.078603) (xy -0.608981 -3.083332) (xy -0.559255 -3.088281) (xy -0.516640 -3.093174)
(xy -0.483435 -3.097733) (xy -0.461941 -3.101682) (xy -0.455701 -3.103605) (xy -0.442045 -3.112818) (xy -0.435156 -3.126955) (xy -0.432376 -3.148118) (xy -0.431756 -3.161679) (xy -0.432057 -3.176250)
(xy -0.433576 -3.193270) (xy -0.436612 -3.214177) (xy -0.441465 -3.240412) (xy -0.448431 -3.273414) (xy -0.457811 -3.314622) (xy -0.469902 -3.365475) (xy -0.485004 -3.427414) (xy -0.503414 -3.501876)
(xy -0.517562 -3.558739) (xy -0.535734 -3.631480) (xy -0.550684 -3.690704) (xy -0.562857 -3.737843) (xy -0.572697 -3.774330) (xy -0.580648 -3.801600) (xy -0.587154 -3.821084) (xy -0.592659 -3.834217)
(xy -0.597607 -3.842431) (xy -0.602442 -3.847161) (xy -0.607609 -3.849838) (xy -0.607779 -3.849904) (xy -0.622823 -3.852525) (xy -0.651312 -3.854507) (xy -0.691309 -3.855852) (xy -0.740876 -3.856566)
(xy -0.798078 -3.856655) (xy -0.860978 -3.856122) (xy -0.927640 -3.854974) (xy -0.996127 -3.853214) (xy -1.064504 -3.850849) (xy -1.116061 -3.848608) (xy -1.285044 -3.840195) (xy -1.444984 -3.831492)
(xy -1.599034 -3.822272) (xy -1.750347 -3.812311) (xy -1.902076 -3.801387) (xy -2.057374 -3.789274) (xy -2.219394 -3.775748) (xy -2.391288 -3.760585) (xy -2.520758 -3.748730) (xy -2.602945 -3.741147)
(xy -2.684137 -3.733733) (xy -2.762346 -3.726664) (xy -2.835583 -3.720117) (xy -2.901859 -3.714268) (xy -2.959186 -3.709294) (xy -3.005575 -3.705371) (xy -3.039036 -3.702676) (xy -3.044152 -3.702288)
(xy -3.117711 -3.696147) (xy -3.177551 -3.689286) (xy -3.225345 -3.680956) (xy -3.262768 -3.670408) (xy -3.291494 -3.656893) (xy -3.313198 -3.639662) (xy -3.329554 -3.617966) (xy -3.342236 -3.591055)
(xy -3.350936 -3.565014) (xy -3.355202 -3.544809) (xy -3.360027 -3.512283) (xy -3.365052 -3.470481) (xy -3.369916 -3.422449) (xy -3.374262 -3.371231) (xy -3.375024 -3.361044) (xy -3.386964 -3.209672)
(xy -3.399935 -3.070062) (xy -3.414437 -2.938595) (xy -3.430968 -2.811649) (xy -3.450025 -2.685602) (xy -3.472107 -2.556833) (xy -3.497712 -2.421722) (xy -3.518055 -2.321155) (xy -3.529674 -2.263592)
(xy -3.540947 -2.205208) (xy -3.551221 -2.149583) (xy -3.559841 -2.100300) (xy -3.566153 -2.060938) (xy -3.568000 -2.047912) (xy -3.572350 -2.006296) (xy -3.576340 -1.949790) (xy -3.579960 -1.878894)
(xy -3.583197 -1.794110) (xy -3.586041 -1.695937) (xy -3.588480 -1.584877) (xy -3.590503 -1.461428) (xy -3.592099 -1.326093) (xy -3.593256 -1.179371) (xy -3.593963 -1.021762) (xy -3.594200 -0.884054)
(xy -3.594485 -0.371109) (xy -3.720499 -0.371109) (xy -3.713255 -0.388201) (xy -3.702385 -0.435802) (xy -3.701095 -0.444604) (xy -3.699689 -0.462676) (xy -3.698321 -0.495472) (xy -3.696999 -0.542318)
(xy -3.695735 -0.602545) (xy -3.694536 -0.675480) (xy -3.693412 -0.760453) (xy -3.692373 -0.856792) (xy -3.691428 -0.963825) (xy -3.690587 -1.080882) (xy -3.689858 -1.207291) (xy -3.689556 -1.270000)
(xy -3.686090 -2.035848) (xy -3.628835 -2.324484) (xy -3.602833 -2.457351) (xy -3.580093 -2.577699) (xy -3.560236 -2.687968) (xy -3.542883 -2.790598) (xy -3.527657 -2.888028) (xy -3.514177 -2.982696)
(xy -3.502066 -3.077043) (xy -3.490944 -3.173507) (xy -3.480433 -3.274527) (xy -3.478863 -3.290454) (xy -3.470265 -3.374337) (xy -3.461866 -3.448626) (xy -3.453816 -3.512213) (xy -3.446269 -3.563990)
(xy -3.439376 -3.602851) (xy -3.433289 -3.627687) (xy -3.432138 -3.630989) (xy -3.427356 -3.651708) (xy -3.433336 -3.665527) (xy -3.451965 -3.675182) (xy -3.465164 -3.678946) (xy -3.507668 -3.692096)
(xy -3.536120 -3.707309) (xy -3.551843 -3.725798) (xy -3.556155 -3.748776) (xy -3.554664 -3.761226) (xy -3.551960 -3.769461) (xy -3.546366 -3.776281) (xy -3.536454 -3.781877) (xy -3.520797 -3.786437)
(xy -3.497967 -3.790153) (xy -3.466536 -3.793213) (xy -3.425077 -3.795808) (xy -3.372163 -3.798126) (xy -3.306365 -3.800359) (xy -3.247086 -3.802108) (xy -3.182487 -3.804023) (xy -3.120840 -3.805999)
(xy -3.064335 -3.807957) (xy -3.015162 -3.809813) (xy -2.975512 -3.811488) (xy -2.947573 -3.812898) (xy -2.936394 -3.813664) (xy -2.911399 -3.815726) (xy -2.875452 -3.818528) (xy -2.832960 -3.821735)
(xy -2.788328 -3.825009) (xy -2.778606 -3.825709) (xy -2.741474 -3.828558) (xy -2.692200 -3.832617) (xy -2.633965 -3.837608) (xy -2.569948 -3.843254) (xy -2.503329 -3.849278) (xy -2.437290 -3.855403)
(xy -2.428394 -3.856241) (xy -2.160197 -3.880397) (xy -1.906563 -3.900837) (xy -1.667121 -3.917581) (xy -1.441501 -3.930650) (xy -1.229332 -3.940062) (xy -1.030244 -3.945839) (xy -0.843865 -3.948000)
(xy -0.729889 -3.947481) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy -0.580267 -1.754184) (xy -0.581514 -1.572055) (xy -0.582896 -1.400845) (xy -0.584407 -1.240926) (xy -0.586040 -1.092672) (xy -0.587790 -0.956454) (xy -0.589649 -0.832644) (xy -0.591610 -0.721617)
(xy -0.593668 -0.623743) (xy -0.595815 -0.539395) (xy -0.598046 -0.468946) (xy -0.600352 -0.412768) (xy -0.602729 -0.371233) (xy -0.605169 -0.344715) (xy -0.605205 -0.344439) (xy -0.611495 -0.318896)
(xy -0.622278 -0.307882) (xy -0.638504 -0.310944) (xy -0.653770 -0.321348) (xy -0.666463 -0.337560) (xy -0.676701 -0.360506) (xy -0.678157 -0.365606) (xy -0.679751 -0.379017) (xy -0.681489 -0.406286)
(xy -0.683320 -0.445876) (xy -0.685195 -0.496253) (xy -0.687064 -0.555880) (xy -0.688876 -0.623222) (xy -0.690582 -0.696743) (xy -0.692131 -0.774909) (xy -0.692841 -0.815878) (xy -0.694976 -0.942155)
(xy -0.697256 -1.071436) (xy -0.699648 -1.202064) (xy -0.702118 -1.332381) (xy -0.704631 -1.460727) (xy -0.707154 -1.585444) (xy -0.709652 -1.704875) (xy -0.712091 -1.817360) (xy -0.714436 -1.921241)
(xy -0.716655 -2.014860) (xy -0.718712 -2.096558) (xy -0.720573 -2.164677) (xy -0.720736 -2.170281) (xy -0.725778 -2.343198) (xy -0.787635 -2.278038) (xy -0.857690 -2.201347) (xy -0.924050 -2.122409)
(xy -0.988271 -2.039052) (xy -1.051915 -1.949103) (xy -1.116540 -1.850390) (xy -1.183705 -1.740742) (xy -1.229482 -1.662545) (xy -1.259170 -1.612033) (xy -1.283367 -1.573673) (xy -1.303541 -1.545881)
(xy -1.321157 -1.527078) (xy -1.337683 -1.515682) (xy -1.354586 -1.510112) (xy -1.372107 -1.508775) (xy -1.401416 -1.511977) (xy -1.431660 -1.522152) (xy -1.465493 -1.540616) (xy -1.505568 -1.568685)
(xy -1.527849 -1.585994) (xy -1.610326 -1.656326) (xy -1.687110 -1.732117) (xy -1.761511 -1.816821) (xy -1.818741 -1.889606) (xy -1.869370 -1.956323) (xy -1.911755 -2.011152) (xy -1.946541 -2.054769)
(xy -1.974373 -2.087855) (xy -1.995896 -2.111087) (xy -2.011756 -2.125143) (xy -2.022597 -2.130703) (xy -2.029064 -2.128445) (xy -2.031803 -2.119048) (xy -2.032000 -2.113935) (xy -2.032587 -2.099423)
(xy -2.034185 -2.073264) (xy -2.036551 -2.039158) (xy -2.039441 -2.000800) (xy -2.039472 -2.000405) (xy -2.041578 -1.970780) (xy -2.044306 -1.928176) (xy -2.047517 -1.874990) (xy -2.051072 -1.813618)
(xy -2.054832 -1.746457) (xy -2.058660 -1.675902) (xy -2.062415 -1.604351) (xy -2.062589 -1.600969) (xy -2.071137 -1.438556) (xy -2.079338 -1.290907) (xy -2.087268 -1.157397) (xy -2.095006 -1.037404)
(xy -2.102630 -0.930303) (xy -2.110219 -0.835470) (xy -2.117849 -0.752281) (xy -2.125600 -0.680113) (xy -2.133550 -0.618340) (xy -2.141776 -0.566340) (xy -2.150357 -0.523488) (xy -2.159370 -0.489160)
(xy -2.168894 -0.462732) (xy -2.179007 -0.443580) (xy -2.189787 -0.431081) (xy -2.201312 -0.424610) (xy -2.209953 -0.423333) (xy -2.224530 -0.429504) (xy -2.231851 -0.438221) (xy -2.236333 -0.455446)
(xy -2.238830 -0.484145) (xy -2.239328 -0.520524) (xy -2.237817 -0.560791) (xy -2.234284 -0.601152) (xy -2.232404 -0.615757) (xy -2.229425 -0.641661) (xy -2.225770 -0.681784) (xy -2.221514 -0.734968)
(xy -2.216734 -0.800057) (xy -2.211505 -0.875894) (xy -2.205902 -0.961322) (xy -2.200002 -1.055184) (xy -2.193880 -1.156324) (xy -2.187612 -1.263584) (xy -2.181273 -1.375807) (xy -2.174939 -1.491836)
(xy -2.174247 -1.504757) (xy -2.166470 -1.647082) (xy -2.159144 -1.774466) (xy -2.152238 -1.887353) (xy -2.145722 -1.986187) (xy -2.139566 -2.071414) (xy -2.133738 -2.143478) (xy -2.128209 -2.202824)
(xy -2.123402 -2.246224) (xy -2.114045 -2.297521) (xy -2.100307 -2.334160) (xy -2.082157 -2.356138) (xy -2.059561 -2.363452) (xy -2.032487 -2.356097) (xy -2.000902 -2.334071) (xy -1.964773 -2.297369)
(xy -1.924068 -2.245988) (xy -1.907479 -2.222736) (xy -1.824434 -2.106332) (xy -1.745678 -2.002055) (xy -1.669538 -1.907839) (xy -1.594343 -1.821619) (xy -1.518421 -1.741327) (xy -1.516150 -1.739023)
(xy -1.486276 -1.709613) (xy -1.458721 -1.684038) (xy -1.435910 -1.664436) (xy -1.420269 -1.652948) (xy -1.416419 -1.651055) (xy -1.403623 -1.650244) (xy -1.390201 -1.656926) (xy -1.374953 -1.672507)
(xy -1.356680 -1.698394) (xy -1.334182 -1.735992) (xy -1.315882 -1.768923) (xy -1.254418 -1.877850) (xy -1.194653 -1.975345) (xy -1.134218 -2.064820) (xy -1.070744 -2.149691) (xy -1.001861 -2.233370)
(xy -0.962442 -2.278303) (xy -0.927698 -2.317605) (xy -0.887578 -2.363724) (xy -0.846470 -2.411576) (xy -0.808760 -2.456075) (xy -0.799712 -2.466878) (xy -0.762100 -2.511209) (xy -0.731760 -2.544831)
(xy -0.706674 -2.569312) (xy -0.684826 -2.586220) (xy -0.664198 -2.597120) (xy -0.642771 -2.603580) (xy -0.619162 -2.607103) (xy -0.574887 -2.611672) (xy -0.580267 -1.754184) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy 1.416074 -2.573229) (xy 1.430249 -2.555754) (xy 1.440093 -2.526748) (xy 1.441464 -2.513429) (xy 1.442747 -2.486324) (xy 1.443917 -2.447040) (xy 1.444946 -2.397186) (xy 1.445806 -2.338369)
(xy 1.446471 -2.272197) (xy 1.446913 -2.200278) (xy 1.447104 -2.124219) (xy 1.447110 -2.112818) (xy 1.447256 -2.037054) (xy 1.447646 -1.965819) (xy 1.448252 -1.900624) (xy 1.449050 -1.842981)
(xy 1.450013 -1.794399) (xy 1.451115 -1.756391) (xy 1.452331 -1.730466) (xy 1.453634 -1.718136) (xy 1.453891 -1.717453) (xy 1.464894 -1.711164) (xy 1.471901 -1.713604) (xy 1.479514 -1.720569)
(xy 1.496374 -1.737572) (xy 1.521278 -1.763348) (xy 1.553022 -1.796635) (xy 1.590403 -1.836167) (xy 1.632214 -1.880681) (xy 1.677254 -1.928913) (xy 1.687233 -1.939636) (xy 1.754307 -2.011336)
(xy 1.818013 -2.078619) (xy 1.877559 -2.140693) (xy 1.932152 -2.196765) (xy 1.980999 -2.246042) (xy 2.023307 -2.287731) (xy 2.058285 -2.321039) (xy 2.085139 -2.345174) (xy 2.103076 -2.359343)
(xy 2.110501 -2.362969) (xy 2.127452 -2.356319) (xy 2.137154 -2.336276) (xy 2.139757 -2.308428) (xy 2.138725 -2.292678) (xy 2.135104 -2.276399) (xy 2.128110 -2.258591) (xy 2.116956 -2.238256)
(xy 2.100857 -2.214395) (xy 2.079029 -2.186009) (xy 2.050685 -2.152099) (xy 2.015040 -2.111667) (xy 1.971310 -2.063714) (xy 1.918707 -2.007240) (xy 1.856448 -1.941247) (xy 1.824804 -1.907898)
(xy 1.757315 -1.836253) (xy 1.699862 -1.773962) (xy 1.652673 -1.721285) (xy 1.615976 -1.678479) (xy 1.589997 -1.645803) (xy 1.576134 -1.625549) (xy 1.569220 -1.612182) (xy 1.567761 -1.600587)
(xy 1.572226 -1.585354) (xy 1.581430 -1.564645) (xy 1.604607 -1.520841) (xy 1.638159 -1.466810) (xy 1.681584 -1.403218) (xy 1.734381 -1.330733) (xy 1.796047 -1.250021) (xy 1.866082 -1.161750)
(xy 1.943984 -1.066586) (xy 2.029251 -0.965196) (xy 2.054891 -0.935181) (xy 2.110331 -0.869728) (xy 2.155741 -0.814354) (xy 2.191833 -0.768114) (xy 2.219321 -0.730060) (xy 2.238918 -0.699249)
(xy 2.251337 -0.674734) (xy 2.251357 -0.674688) (xy 2.261330 -0.639246) (xy 2.261412 -0.607143) (xy 2.251750 -0.582238) (xy 2.247628 -0.577386) (xy 2.234612 -0.568613) (xy 2.220168 -0.568582)
(xy 2.202755 -0.578279) (xy 2.180833 -0.598691) (xy 2.152862 -0.630804) (xy 2.140632 -0.645898) (xy 2.118675 -0.672801) (xy 2.089172 -0.708140) (xy 2.054757 -0.748805) (xy 2.018063 -0.791684)
(xy 1.981725 -0.833665) (xy 1.980456 -0.835121) (xy 1.865008 -0.971084) (xy 1.754299 -1.108968) (xy 1.644578 -1.253533) (xy 1.572843 -1.352174) (xy 1.533619 -1.406302) (xy 1.502352 -1.448041)
(xy 1.479143 -1.477267) (xy 1.464091 -1.493858) (xy 1.457295 -1.497688) (xy 1.456904 -1.496698) (xy 1.455985 -1.483631) (xy 1.454554 -1.457132) (xy 1.452692 -1.419154) (xy 1.450483 -1.371647)
(xy 1.448009 -1.316563) (xy 1.445353 -1.255853) (xy 1.442598 -1.191468) (xy 1.439826 -1.125359) (xy 1.437121 -1.059478) (xy 1.434566 -0.995777) (xy 1.432242 -0.936205) (xy 1.430234 -0.882715)
(xy 1.428623 -0.837258) (xy 1.427683 -0.808181) (xy 1.425295 -0.737040) (xy 1.422581 -0.680003) (xy 1.419074 -0.635785) (xy 1.414308 -0.603096) (xy 1.407814 -0.580649) (xy 1.399126 -0.567157)
(xy 1.387777 -0.561331) (xy 1.373299 -0.561883) (xy 1.355225 -0.567527) (xy 1.342328 -0.572878) (xy 1.322180 -0.587282) (xy 1.313598 -0.607510) (xy 1.312718 -0.620787) (xy 1.312426 -0.647174)
(xy 1.312659 -0.684405) (xy 1.313355 -0.730210) (xy 1.314454 -0.782320) (xy 1.315894 -0.838467) (xy 1.317614 -0.896382) (xy 1.319552 -0.953796) (xy 1.321647 -1.008441) (xy 1.323837 -1.058048)
(xy 1.326062 -1.100348) (xy 1.327562 -1.123757) (xy 1.330061 -1.165367) (xy 1.332685 -1.220905) (xy 1.335392 -1.288910) (xy 1.338141 -1.367917) (xy 1.340890 -1.456462) (xy 1.343597 -1.553082)
(xy 1.346221 -1.656314) (xy 1.348719 -1.764693) (xy 1.351052 -1.876756) (xy 1.353176 -1.991039) (xy 1.354499 -2.070484) (xy 1.356166 -2.171146) (xy 1.357798 -2.257510) (xy 1.359491 -2.330672)
(xy 1.361337 -2.391728) (xy 1.363429 -2.441772) (xy 1.365862 -2.481902) (xy 1.368728 -2.513211) (xy 1.372121 -2.536797) (xy 1.376134 -2.553755) (xy 1.380861 -2.565180) (xy 1.386395 -2.572168)
(xy 1.392829 -2.575815) (xy 1.397673 -2.576932) (xy 1.416074 -2.573229) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy 0.413839 -1.778171) (xy 0.487472 -1.762120) (xy 0.552827 -1.733891) (xy 0.610616 -1.693201) (xy 0.661555 -1.639769) (xy 0.692947 -1.595534) (xy 0.728063 -1.525928) (xy 0.749524 -1.449748)
(xy 0.757294 -1.367599) (xy 0.751337 -1.280085) (xy 0.731616 -1.187811) (xy 0.719845 -1.149644) (xy 0.679778 -1.046656) (xy 0.630809 -0.949135) (xy 0.574189 -0.858661) (xy 0.511166 -0.776816)
(xy 0.442992 -0.705178) (xy 0.370915 -0.645328) (xy 0.296185 -0.598846) (xy 0.276609 -0.589207) (xy 0.229472 -0.574371) (xy 0.177682 -0.569812) (xy 0.127353 -0.575725) (xy 0.102113 -0.583671)
(xy 0.062884 -0.606703) (xy 0.024317 -0.642488) (xy -0.011571 -0.688444) (xy -0.042760 -0.741990) (xy -0.067062 -0.800039) (xy -0.073472 -0.820456) (xy -0.078089 -0.840336) (xy -0.081205 -0.862769)
(xy -0.083110 -0.890842) (xy -0.084093 -0.927643) (xy -0.084445 -0.976259) (xy -0.084462 -0.985212) (xy -0.083487 -1.057880) (xy 0.016518 -1.057880) (xy 0.018467 -0.989939) (xy 0.022947 -0.926482)
(xy 0.029926 -0.871194) (xy 0.038403 -0.831167) (xy 0.051078 -0.798647) (xy 0.070429 -0.763815) (xy 0.093123 -0.731757) (xy 0.115825 -0.707559) (xy 0.123151 -0.701891) (xy 0.152511 -0.689175)
(xy 0.187591 -0.687778) (xy 0.229873 -0.697839) (xy 0.273879 -0.716122) (xy 0.334098 -0.752854) (xy 0.392535 -0.804598) (xy 0.448925 -0.871050) (xy 0.503007 -0.951902) (xy 0.549789 -1.037325)
(xy 0.590963 -1.126097) (xy 0.621283 -1.206263) (xy 0.640579 -1.277284) (xy 0.648679 -1.338622) (xy 0.648942 -1.350818) (xy 0.641794 -1.421635) (xy 0.620651 -1.486091) (xy 0.585681 -1.543838)
(xy 0.537053 -1.594525) (xy 0.527967 -1.601996) (xy 0.496740 -1.624584) (xy 0.473047 -1.635825) (xy 0.454683 -1.636294) (xy 0.439441 -1.626566) (xy 0.438292 -1.625366) (xy 0.428336 -1.616769)
(xy 0.415049 -1.610434) (xy 0.395420 -1.605624) (xy 0.366441 -1.601604) (xy 0.325104 -1.597637) (xy 0.324905 -1.597620) (xy 0.265315 -1.584985) (xy 0.209117 -1.558530) (xy 0.157727 -1.519701)
(xy 0.112559 -1.469946) (xy 0.075028 -1.410711) (xy 0.046548 -1.343443) (xy 0.034613 -1.300787) (xy 0.026146 -1.251759) (xy 0.020327 -1.192475) (xy 0.017128 -1.126620) (xy 0.016518 -1.057880)
(xy -0.083487 -1.057880) (xy -0.083015 -1.093007) (xy -0.078110 -1.187172) (xy -0.069390 -1.269155) (xy -0.056497 -1.340402) (xy -0.039077 -1.402362) (xy -0.016772 -1.456483) (xy 0.010773 -1.504212)
(xy 0.043916 -1.546997) (xy 0.057430 -1.561617) (xy 0.079396 -1.585522) (xy 0.096504 -1.606331) (xy 0.106330 -1.620986) (xy 0.107757 -1.625161) (xy 0.102547 -1.637308) (xy 0.089535 -1.653746)
(xy 0.084326 -1.659023) (xy 0.066985 -1.682189) (xy 0.064652 -1.703714) (xy 0.077006 -1.723356) (xy 0.103725 -1.740875) (xy 0.144488 -1.756030) (xy 0.198972 -1.768580) (xy 0.238888 -1.774863)
(xy 0.331216 -1.782325) (xy 0.413839 -1.778171) )(layer F.SilkS) (width 0.010000)
)
(fp_poly (pts (xy 0.882644 -4.062544) (xy 0.891811 -4.059054) (xy 0.916301 -4.046474) (xy 0.930145 -4.031899) (xy 0.935572 -4.019506) (xy 0.943411 -3.999666) (xy 0.953654 -3.986888) (xy 0.970030 -3.978818)
(xy 0.996269 -3.973106) (xy 1.013170 -3.970552) (xy 1.027303 -3.969605) (xy 1.056192 -3.968628) (xy 1.099198 -3.967629) (xy 1.155684 -3.966613) (xy 1.225012 -3.965587) (xy 1.306543 -3.964557)
(xy 1.399639 -3.963530) (xy 1.503662 -3.962513) (xy 1.617975 -3.961511) (xy 1.741939 -3.960532) (xy 1.874915 -3.959582) (xy 2.016266 -3.958668) (xy 2.165354 -3.957795) (xy 2.321541 -3.956970)
(xy 2.370666 -3.956729) (xy 2.541404 -3.955885) (xy 2.697385 -3.955074) (xy 2.839246 -3.954287) (xy 2.967622 -3.953517) (xy 3.083152 -3.952755) (xy 3.186471 -3.951993) (xy 3.278217 -3.951223)
(xy 3.359025 -3.950437) (xy 3.429534 -3.949627) (xy 3.490378 -3.948786) (xy 3.542196 -3.947904) (xy 3.585624 -3.946974) (xy 3.621298 -3.945989) (xy 3.649856 -3.944939) (xy 3.671933 -3.943817)
(xy 3.688167 -3.942614) (xy 3.699195 -3.941324) (xy 3.705652 -3.939937) (xy 3.705877 -3.939861) (xy 3.734617 -3.923702) (xy 3.750326 -3.900782) (xy 3.752684 -3.873022) (xy 3.741372 -3.842344)
(xy 3.725671 -3.820754) (xy 3.712765 -3.803990) (xy 3.703006 -3.785372) (xy 3.695794 -3.762247) (xy 3.690528 -3.731963) (xy 3.686607 -3.691868) (xy 3.683430 -3.639309) (xy 3.683115 -3.632969)
(xy 3.674635 -3.517752) (xy 3.660952 -3.407897) (xy 3.642638 -3.307886) (xy 3.640136 -3.296668) (xy 3.631236 -3.250908) (xy 3.624920 -3.201896) (xy 3.621156 -3.147687) (xy 3.619911 -3.086336)
(xy 3.621150 -3.015898) (xy 3.624842 -2.934429) (xy 3.630951 -2.839983) (xy 3.632059 -2.824787) (xy 3.640968 -2.694518) (xy 3.648700 -2.561913) (xy 3.655245 -2.428324) (xy 3.660590 -2.295106)
(xy 3.664725 -2.163609) (xy 3.667638 -2.035186) (xy 3.669317 -1.911191) (xy 3.669752 -1.792976) (xy 3.668931 -1.681893) (xy 3.666842 -1.579295) (xy 3.663474 -1.486535) (xy 3.658816 -1.404964)
(xy 3.652857 -1.335937) (xy 3.645585 -1.280804) (xy 3.645060 -1.277696) (xy 3.639765 -1.248605) (xy 3.632015 -1.208332) (xy 3.622577 -1.160748) (xy 3.612217 -1.109726) (xy 3.603150 -1.066030)
(xy 3.587130 -0.986511) (xy 3.574408 -0.916630) (xy 3.565112 -0.857352) (xy 3.559371 -0.809645) (xy 3.557312 -0.774474) (xy 3.559065 -0.752807) (xy 3.560919 -0.748046) (xy 3.572111 -0.739079)
(xy 3.593362 -0.728473) (xy 3.617657 -0.719357) (xy 3.652679 -0.705626) (xy 3.672925 -0.691538) (xy 3.679013 -0.676498) (xy 3.674675 -0.664259) (xy 3.661589 -0.652446) (xy 3.643926 -0.643858)
(xy 3.632345 -0.642498) (xy 3.607270 -0.641167) (xy 3.570602 -0.639885) (xy 3.524243 -0.638671) (xy 3.470092 -0.637544) (xy 3.410049 -0.636524) (xy 3.346017 -0.635629) (xy 3.279894 -0.634881)
(xy 3.213583 -0.634297) (xy 3.148982 -0.633897) (xy 3.087994 -0.633701) (xy 3.032518 -0.633729) (xy 2.984456 -0.633998) (xy 2.945707 -0.634529) (xy 2.918172 -0.635342) (xy 2.904621 -0.636319)
(xy 2.888080 -0.640755) (xy 2.879737 -0.651268) (xy 2.875741 -0.668129) (xy 2.872518 -0.695426) (xy 2.869548 -0.736927) (xy 2.866851 -0.791445) (xy 2.864446 -0.857789) (xy 2.862353 -0.934774)
(xy 2.860590 -1.021210) (xy 2.859178 -1.115910) (xy 2.858136 -1.217685) (xy 2.857483 -1.325348) (xy 2.857239 -1.437710) (xy 2.857423 -1.553583) (xy 2.858054 -1.671779) (xy 2.858478 -1.724121)
(xy 2.860130 -1.890006) (xy 2.862003 -2.041374) (xy 2.864130 -2.179100) (xy 2.866547 -2.304059) (xy 2.869289 -2.417126) (xy 2.872389 -2.519178) (xy 2.875882 -2.611090) (xy 2.879804 -2.693736)
(xy 2.884187 -2.767992) (xy 2.889067 -2.834734) (xy 2.894479 -2.894836) (xy 2.900456 -2.949175) (xy 2.907034 -2.998626) (xy 2.909356 -3.014108) (xy 2.915170 -3.053202) (xy 2.919985 -3.088291)
(xy 2.923333 -3.115775) (xy 2.924749 -3.132050) (xy 2.924767 -3.132982) (xy 2.924848 -3.152541) (xy 2.761615 -3.135282) (xy 2.698919 -3.128956) (xy 2.633231 -3.122957) (xy 2.563218 -3.117202)
(xy 2.487544 -3.111607) (xy 2.404875 -3.106089) (xy 2.313878 -3.100563) (xy 2.213218 -3.094946) (xy 2.101560 -3.089154) (xy 1.977571 -3.083103) (xy 1.839915 -3.076711) (xy 1.797242 -3.074781)
(xy 1.772207 -3.073740) (xy 1.733538 -3.072245) (xy 1.682988 -3.070359) (xy 1.622308 -3.068146) (xy 1.553252 -3.065668) (xy 1.477570 -3.062989) (xy 1.397014 -3.060171) (xy 1.313337 -3.057278)
(xy 1.258786 -3.055410) (xy 0.812694 -3.040195) (xy 0.794932 -3.061415) (xy 0.763630 -3.105415) (xy 0.742689 -3.149234) (xy 0.735083 -3.178848) (xy 0.734188 -3.195589) (xy 0.734205 -3.225313)
(xy 0.735065 -3.265640) (xy 0.735733 -3.285465) (xy 0.823576 -3.285465) (xy 0.828032 -3.241919) (xy 0.841901 -3.209577) (xy 0.865935 -3.186914) (xy 0.874583 -3.182099) (xy 0.883088 -3.178327)
(xy 0.892983 -3.175227) (xy 0.905838 -3.172716) (xy 0.923220 -3.170713) (xy 0.946696 -3.169135) (xy 0.977835 -3.167899) (xy 1.018204 -3.166925) (xy 1.069371 -3.166129) (xy 1.132904 -3.165429)
(xy 1.204576 -3.164791) (xy 1.490003 -3.165601) (xy 1.776652 -3.172662) (xy 2.061314 -3.185795) (xy 2.340782 -3.204820) (xy 2.611848 -3.229561) (xy 2.840182 -3.255828) (xy 2.891314 -3.262298)
(xy 2.937329 -3.268068) (xy 2.976038 -3.272866) (xy 3.005248 -3.276424) (xy 3.022771 -3.278470) (xy 3.026833 -3.278861) (xy 3.029918 -3.274161) (xy 3.031462 -3.259568) (xy 3.031419 -3.234444)
(xy 3.029741 -3.198145) (xy 3.026381 -3.150032) (xy 3.021294 -3.089464) (xy 3.014431 -3.015799) (xy 3.005745 -2.928396) (xy 2.995191 -2.826615) (xy 2.990512 -2.782454) (xy 2.987639 -2.749642)
(xy 2.984543 -2.703979) (xy 2.981351 -2.648004) (xy 2.978189 -2.584258) (xy 2.975184 -2.515278) (xy 2.972461 -2.443605) (xy 2.970227 -2.374515) (xy 2.968197 -2.293637) (xy 2.966616 -2.205797)
(xy 2.965466 -2.112157) (xy 2.964729 -2.013879) (xy 2.964387 -1.912126) (xy 2.964421 -1.808061) (xy 2.964815 -1.702847) (xy 2.965549 -1.597647) (xy 2.966606 -1.493622) (xy 2.967969 -1.391937)
(xy 2.969618 -1.293754) (xy 2.971536 -1.200235) (xy 2.973706 -1.112543) (xy 2.976108 -1.031842) (xy 2.978726 -0.959293) (xy 2.981541 -0.896060) (xy 2.984535 -0.843306) (xy 2.987691 -0.802192)
(xy 2.990989 -0.773883) (xy 2.994413 -0.759540) (xy 2.995207 -0.758348) (xy 3.003440 -0.757177) (xy 3.024992 -0.755516) (xy 3.057802 -0.753485) (xy 3.099805 -0.751203) (xy 3.148940 -0.748789)
(xy 3.198297 -0.746572) (xy 3.252441 -0.744152) (xy 3.301610 -0.741782) (xy 3.343679 -0.739577) (xy 3.376525 -0.737655) (xy 3.398023 -0.736132) (xy 3.405909 -0.735199) (xy 3.417346 -0.732791)
(xy 3.424593 -0.738147) (xy 3.430730 -0.754407) (xy 3.433084 -0.762875) (xy 3.441432 -0.796955) (xy 3.451759 -0.844104) (xy 3.463669 -0.902182) (xy 3.476763 -0.969050) (xy 3.490644 -1.042566)
(xy 3.504913 -1.120593) (xy 3.519173 -1.200988) (xy 3.533026 -1.281613) (xy 3.546075 -1.360327) (xy 3.557402 -1.431636) (xy 3.565246 -1.495353) (xy 3.570829 -1.570937) (xy 3.574146 -1.658837)
(xy 3.575197 -1.759504) (xy 3.573978 -1.873384) (xy 3.570486 -2.000928) (xy 3.564720 -2.142585) (xy 3.556677 -2.298803) (xy 3.552051 -2.378363) (xy 3.545127 -2.498841) (xy 3.539626 -2.607034)
(xy 3.535437 -2.705975) (xy 3.532453 -2.798699) (xy 3.530565 -2.888238) (xy 3.529665 -2.977625) (xy 3.529569 -3.005666) (xy 3.529060 -3.267363) (xy 3.554921 -3.417454) (xy 3.563456 -3.469541)
(xy 3.571265 -3.521944) (xy 3.577811 -3.570694) (xy 3.582558 -3.611824) (xy 3.584841 -3.638893) (xy 3.586066 -3.679477) (xy 3.583379 -3.707451) (xy 3.575387 -3.725393) (xy 3.560697 -3.735879)
(xy 3.537916 -3.741486) (xy 3.528745 -3.742664) (xy 3.505039 -3.747122) (xy 3.486746 -3.753658) (xy 3.482883 -3.756117) (xy 3.472444 -3.773337) (xy 3.473638 -3.793322) (xy 3.485788 -3.809592)
(xy 3.488651 -3.811388) (xy 3.498049 -3.817406) (xy 3.497156 -3.821146) (xy 3.484009 -3.824301) (xy 3.471333 -3.826326) (xy 3.444873 -3.829157) (xy 3.404059 -3.831835) (xy 3.349928 -3.834345)
(xy 3.283519 -3.836673) (xy 3.205871 -3.838805) (xy 3.118022 -3.840726) (xy 3.021011 -3.842421) (xy 2.915876 -3.843877) (xy 2.803656 -3.845080) (xy 2.685389 -3.846013) (xy 2.562114 -3.846665)
(xy 2.434869 -3.847019) (xy 2.304693 -3.847061) (xy 2.172624 -3.846778) (xy 2.039701 -3.846154) (xy 2.039697 -3.846154) (xy 1.914750 -3.845288) (xy 1.792699 -3.844215) (xy 1.674484 -3.842957)
(xy 1.561043 -3.841532) (xy 1.453315 -3.839961) (xy 1.352241 -3.838264) (xy 1.258758 -3.836460) (xy 1.173806 -3.834570) (xy 1.098323 -3.832613) (xy 1.033250 -3.830609) (xy 0.979525 -3.828578)
(xy 0.938088 -3.826539) (xy 0.909876 -3.824514) (xy 0.895830 -3.822521) (xy 0.894503 -3.821917) (xy 0.892426 -3.813444) (xy 0.888759 -3.791827) (xy 0.883786 -3.759202) (xy 0.877789 -3.717703)
(xy 0.871049 -3.669468) (xy 0.863850 -3.616630) (xy 0.856474 -3.561326) (xy 0.849203 -3.505691) (xy 0.842319 -3.451861) (xy 0.836105 -3.401972) (xy 0.830843 -3.358159) (xy 0.826816 -3.322557)
(xy 0.824306 -3.297303) (xy 0.823576 -3.285465) (xy 0.735733 -3.285465) (xy 0.736703 -3.314190) (xy 0.739049 -3.368584) (xy 0.742038 -3.426441) (xy 0.742181 -3.429000) (xy 0.745919 -3.496753)
(xy 0.749834 -3.570070) (xy 0.753692 -3.644404) (xy 0.757260 -3.715209) (xy 0.760303 -3.777939) (xy 0.761789 -3.810000) (xy 0.764448 -3.860827) (xy 0.767596 -3.908115) (xy 0.770997 -3.949098)
(xy 0.774413 -3.981012) (xy 0.777607 -4.001090) (xy 0.778441 -4.004251) (xy 0.795116 -4.039913) (xy 0.817967 -4.061480) (xy 0.847106 -4.069005) (xy 0.882644 -4.062544) )(layer F.SilkS) (width 0.010000)
)
)

2560
kicad_pcb/logic_block.sch Normal file

File diff suppressed because it is too large Load Diff

1004
kicad_pcb/lutd.sch Normal file

File diff suppressed because it is too large Load Diff

3
kicad_pcb/sym-lib-table Normal file
View File

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name ttl-fpga-rescue)(type Legacy)(uri ${KIPRJMOD}/ttl-fpga-rescue.lib)(options "")(descr ""))
)

View File

@ -0,0 +1,438 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 4xxx_4066
#
DEF 4xxx_4066 U 0 40 Y Y 5 L N
F0 "U" -300 350 50 H V C CNN
F1 "4xxx_4066" -300 -350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 4066
$FPLIST
DIP?14*
$ENDFPLIST
DRAW
S -200 300 200 -300 5 1 10 f
P 2 1 0 6 0 50 0 100 N
P 4 1 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 1 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 2 0 6 0 50 0 100 N
P 4 2 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 2 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 3 0 6 0 50 0 100 N
P 4 3 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 3 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 4 0 6 0 50 0 100 N
P 4 4 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 4 0 0 -100 100 100 0 -100 -100 -100 100 f
X ~ 1 -300 0 200 R 50 50 1 0 P
X ~ 13 0 300 200 D 50 50 1 0 I
X ~ 2 300 0 200 L 50 50 1 0 P
X ~ 3 300 0 200 L 50 50 2 0 P
X ~ 4 -300 0 200 R 50 50 2 0 P
X ~ 5 0 300 200 D 50 50 2 0 I
X ~ 6 0 300 200 D 50 50 3 0 I
X ~ 8 -300 0 200 R 50 50 3 0 P
X ~ 9 300 0 200 L 50 50 3 0 P
X ~ 10 300 0 200 L 50 50 4 0 P
X ~ 11 -300 0 200 R 50 50 4 0 P
X ~ 12 0 300 200 D 50 50 4 0 I
X VDD 14 0 500 200 D 50 50 5 0 W
X VSS 7 0 -500 200 U 50 50 5 0 W
ENDDRAW
ENDDEF
#
# 74xx_74LS174
#
DEF 74xx_74LS174 U 0 40 Y Y 1 L N
F0 "U" -300 550 50 H V C CNN
F1 "74xx_74LS174" -300 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP?16*
$ENDFPLIST
DRAW
S -300 500 300 -600 1 1 10 f
X ~Mr 1 -500 -500 200 R 50 50 1 0 I
X Q3 10 500 100 200 L 50 50 1 0 O
X D3 11 -500 100 200 R 50 50 1 0 I
X Q4 12 500 0 200 L 50 50 1 0 O
X D4 13 -500 0 200 R 50 50 1 0 I
X D5 14 -500 -100 200 R 50 50 1 0 I
X Q5 15 500 -100 200 L 50 50 1 0 O
X VCC 16 0 700 200 D 50 50 1 0 W
X Q0 2 500 400 200 L 50 50 1 0 O
X D0 3 -500 400 200 R 50 50 1 0 I
X D1 4 -500 300 200 R 50 50 1 0 I
X Q1 5 500 300 200 L 50 50 1 0 O
X D2 6 -500 200 200 R 50 50 1 0 I
X Q2 7 500 200 200 L 50 50 1 0 O
X GND 8 0 -800 200 U 50 50 1 0 W
X Cp 9 -500 -300 200 R 50 50 1 0 I C
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74157
#
DEF 74xx_IEEE_74157 U 0 30 Y Y 1 F N
F0 "U" 300 400 50 H V C CNN
F1 "74xx_IEEE_74157" 250 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 100 60 0 0 0 MUX Normal 0 C C
S -250 -400 250 -600 0 0 0 N
S -250 -200 250 -400 0 0 0 N
S -250 0 250 -200 0 0 0 N
S -250 200 250 0 0 0 0 N
P 9 0 0 0 -200 200 -200 250 -250 250 -250 500 250 500 250 250 200 250 200 200 200 200 N
X VCC 16 150 500 0 D 50 50 0 0 W N
X GND 8 0 500 0 D 50 50 0 0 W N
X A/B 1 -550 300 300 R 50 50 1 1 I
X I1d 10 -550 -550 300 R 50 50 1 1 I
X I0d 11 -550 -450 300 R 50 50 1 1 I
X Qc 12 550 -300 300 L 50 50 1 1 O
X I1c 13 -550 -350 300 R 50 50 1 1 I
X I0c 14 -550 -250 300 R 50 50 1 1 I
X ~EN 15 -550 400 300 R 50 50 1 1 I I
X I0a 2 -550 150 300 R 50 50 1 1 I
X I1a 3 -550 50 300 R 50 50 1 1 I
X Qa 4 550 100 300 L 50 50 1 1 O
X I0b 5 -550 -50 300 R 50 50 1 1 I
X I1b 6 -550 -150 300 R 50 50 1 1 I
X Qb 7 550 -100 300 L 50 50 1 1 O
X Qd 9 550 -500 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74164
#
DEF 74xx_IEEE_74164 U 0 30 Y Y 1 F N
F0 "U" 350 250 50 H V C CNN
F1 "74xx_IEEE_74164" 250 -900 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 -170 -40 60 0 0 0 & Normal 0 C C
S -250 -750 250 -850 0 1 0 N
S -250 -650 250 -750 0 1 0 N
S -250 -550 250 -650 0 1 0 N
S -250 -450 250 -550 0 1 0 N
S -250 -350 250 -450 0 1 0 N
S -250 -250 250 -350 0 1 0 N
S -250 -150 250 -250 0 1 0 N
S -250 50 250 -150 0 1 0 N
P 3 0 1 0 -100 50 -100 -150 -100 -150 N
P 9 0 1 0 -200 50 -200 100 -250 100 -250 350 250 350 250 100 200 100 200 50 200 50 N
X A 1 -550 0 300 R 50 50 1 1 I
X Qe 10 550 -500 300 L 50 50 1 1 O
X Qf 11 550 -600 300 L 50 50 1 1 O
X Qg 12 550 -700 300 L 50 50 1 1 O
X Qh 13 550 -800 300 L 50 50 1 1 O
X Vdd 14 200 350 0 D 50 50 1 1 W N
X B 2 -550 -100 300 R 50 50 1 1 I
X Qa 3 550 -50 300 L 50 50 1 1 O
X Qb 4 550 -200 300 L 50 50 1 1 O
X Qc 5 550 -300 300 L 50 50 1 1 O
X Qd 6 550 -400 300 L 50 50 1 1 O
X Vss 7 0 350 0 D 50 50 1 1 W N
X CK 8 -550 150 300 R 50 50 1 1 I C
X ~R 9 -550 250 300 R 50 50 1 1 I I
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74251
#
DEF 74xx_IEEE_74251 U 0 30 Y Y 1 F N
F0 "U" 300 600 50 H V C CNN
F1 "74xx_IEEE_74251" 350 -800 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 250 50 0 0 0 MUX Normal 0 C C
S -250 650 250 -700 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 380 20 380 50 320 80 380 80 380 N
X VCC 16 0 650 0 D 50 50 0 0 W N
X GND 8 0 -700 0 U 50 50 0 0 W N
X I3 1 -550 -200 300 R 50 50 1 1 I
X S1 10 -550 350 300 R 50 50 1 1 I
X S0 11 -550 450 300 R 50 50 1 1 I
X I7 12 -550 -600 300 R 50 50 1 1 I
X I6 13 -550 -500 300 R 50 50 1 1 I
X I5 14 -550 -400 300 R 50 50 1 1 I
X I4 15 -550 -300 300 R 50 50 1 1 I
X I2 2 -550 -100 300 R 50 50 1 1 I
X I1 3 -550 0 300 R 50 50 1 1 I
X I0 4 -550 100 300 R 50 50 1 1 I
X Q 5 550 350 300 L 50 50 1 1 T
X ~Q 6 550 -350 300 L 50 50 1 1 T I
X ~E 7 -550 550 300 R 50 50 1 1 I I
X S2 9 -550 250 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 74xx_IEEE_74253
#
DEF 74xx_IEEE_74253 U 0 30 Y Y 1 F N
F0 "U" 300 650 50 H V C CNN
F1 "74xx_IEEE_74253" 150 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 300 60 0 0 0 MUX Normal 0 C C
S -250 -100 250 -600 0 0 0 N
S -250 450 250 -100 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 180 20 180 50 120 80 180 80 180 N
P 9 0 0 0 -200 450 -200 500 -250 500 -250 750 250 750 250 500 200 500 200 450 200 450 N
X VCC 16 150 750 0 D 50 50 0 0 W N
X GND 8 0 750 0 D 50 50 0 0 W N
X ~ENa 1 -550 350 300 R 50 50 1 1 I I
X I0b 10 -550 -250 300 R 50 50 1 1 I
X I1b 11 -550 -350 300 R 50 50 1 1 I
X I2b 12 -550 -450 300 R 50 50 1 1 I
X I3b 13 -550 -550 300 R 50 50 1 1 I
X A 14 -550 650 300 R 50 50 1 1 I
X ~ENb 15 -550 -150 300 R 50 50 1 1 I I
X B 2 -550 550 300 R 50 50 1 1 I
X I3a 3 -550 -50 300 R 50 50 1 1 I
X I2a 4 -550 50 300 R 50 50 1 1 I
X I1a 5 -550 150 300 R 50 50 1 1 I
X I0a 6 -550 250 300 R 50 50 1 1 I
X Qa 7 550 150 300 L 50 50 1 1 T
X Qb 9 550 -350 300 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# Connector_Conn_01x12_Female
#
DEF Connector_Conn_01x12_Female J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Connector_Conn_01x12_Female" 0 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
A 0 -600 20 901 -901 1 1 6 N 0 -580 0 -620
A 0 -500 20 901 -901 1 1 6 N 0 -480 0 -520
A 0 -400 20 901 -901 1 1 6 N 0 -380 0 -420
A 0 -300 20 901 -901 1 1 6 N 0 -280 0 -320
A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
A 0 100 20 901 -901 1 1 6 N 0 120 0 80
A 0 200 20 901 -901 1 1 6 N 0 220 0 180
A 0 300 20 901 -901 1 1 6 N 0 320 0 280
A 0 400 20 901 -901 1 1 6 N 0 420 0 380
A 0 500 20 901 -901 1 1 6 N 0 520 0 480
P 2 1 1 6 -50 -600 -20 -600 N
P 2 1 1 6 -50 -500 -20 -500 N
P 2 1 1 6 -50 -400 -20 -400 N
P 2 1 1 6 -50 -300 -20 -300 N
P 2 1 1 6 -50 -200 -20 -200 N
P 2 1 1 6 -50 -100 -20 -100 N
P 2 1 1 6 -50 0 -20 0 N
P 2 1 1 6 -50 100 -20 100 N
P 2 1 1 6 -50 200 -20 200 N
P 2 1 1 6 -50 300 -20 300 N
P 2 1 1 6 -50 400 -20 400 N
P 2 1 1 6 -50 500 -20 500 N
X Pin_1 1 -200 500 150 R 50 50 1 1 P
X Pin_10 10 -200 -400 150 R 50 50 1 1 P
X Pin_11 11 -200 -500 150 R 50 50 1 1 P
X Pin_12 12 -200 -600 150 R 50 50 1 1 P
X Pin_2 2 -200 400 150 R 50 50 1 1 P
X Pin_3 3 -200 300 150 R 50 50 1 1 P
X Pin_4 4 -200 200 150 R 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 -200 0 150 R 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 -200 -200 150 R 50 50 1 1 P
X Pin_9 9 -200 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Conn_01x12_Male
#
DEF Connector_Conn_01x12_Male J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Connector_Conn_01x12_Male" 0 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S 34 -595 0 -605 1 1 6 F
S 34 -495 0 -505 1 1 6 F
S 34 -395 0 -405 1 1 6 F
S 34 -295 0 -305 1 1 6 F
S 34 -195 0 -205 1 1 6 F
S 34 -95 0 -105 1 1 6 F
S 34 5 0 -5 1 1 6 F
S 34 105 0 95 1 1 6 F
S 34 205 0 195 1 1 6 F
S 34 305 0 295 1 1 6 F
S 34 405 0 395 1 1 6 F
S 34 505 0 495 1 1 6 F
P 2 1 1 6 50 -600 34 -600 N
P 2 1 1 6 50 -500 34 -500 N
P 2 1 1 6 50 -400 34 -400 N
P 2 1 1 6 50 -300 34 -300 N
P 2 1 1 6 50 -200 34 -200 N
P 2 1 1 6 50 -100 34 -100 N
P 2 1 1 6 50 0 34 0 N
P 2 1 1 6 50 100 34 100 N
P 2 1 1 6 50 200 34 200 N
P 2 1 1 6 50 300 34 300 N
P 2 1 1 6 50 400 34 400 N
P 2 1 1 6 50 500 34 500 N
X Pin_1 1 200 500 150 L 50 50 1 1 P
X Pin_10 10 200 -400 150 L 50 50 1 1 P
X Pin_11 11 200 -500 150 L 50 50 1 1 P
X Pin_12 12 200 -600 150 L 50 50 1 1 P
X Pin_2 2 200 400 150 L 50 50 1 1 P
X Pin_3 3 200 300 150 L 50 50 1 1 P
X Pin_4 4 200 200 150 L 50 50 1 1 P
X Pin_5 5 200 100 150 L 50 50 1 1 P
X Pin_6 6 200 0 150 L 50 50 1 1 P
X Pin_7 7 200 -100 150 L 50 50 1 1 P
X Pin_8 8 200 -200 150 L 50 50 1 1 P
X Pin_9 9 200 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Schottky
#
DEF Device_D_Schottky D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_D_Schottky" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_GNDD
#
DEF power_GNDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GNDD" 0 -125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -50 -60 50 -80 0 1 10 F
P 2 0 1 0 0 0 0 -60 N
X GNDD 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VCC
#
DEF power_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

View File

@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

View File

@ -0,0 +1,236 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 4066-4xxx
#
DEF 4066-4xxx U 0 40 Y Y 5 L N
F0 "U" -300 350 50 H V C CNN
F1 "4066-4xxx" -300 -350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP?14*
$ENDFPLIST
DRAW
S -200 300 200 -300 5 1 10 f
P 2 1 0 6 0 50 0 100 N
P 4 1 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 1 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 2 0 6 0 50 0 100 N
P 4 2 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 2 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 3 0 6 0 50 0 100 N
P 4 3 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 3 0 0 -100 100 100 0 -100 -100 -100 100 f
P 2 4 0 6 0 50 0 100 N
P 4 4 0 0 -100 0 100 100 100 -100 -100 0 f
P 4 4 0 0 -100 100 100 0 -100 -100 -100 100 f
X ~ 1 -300 0 200 R 50 50 1 0 P
X ~ 13 0 300 200 D 50 50 1 0 I
X ~ 2 300 0 200 L 50 50 1 0 P
X ~ 3 300 0 200 L 50 50 2 0 P
X ~ 4 -300 0 200 R 50 50 2 0 P
X ~ 5 0 300 200 D 50 50 2 0 I
X ~ 6 0 300 200 D 50 50 3 0 I
X ~ 8 -300 0 200 R 50 50 3 0 P
X ~ 9 300 0 200 L 50 50 3 0 P
X ~ 10 300 0 200 L 50 50 4 0 P
X ~ 11 -300 0 200 R 50 50 4 0 P
X ~ 12 0 300 200 D 50 50 4 0 I
X VDD 14 0 500 200 D 50 50 5 0 W
X VSS 7 0 -500 200 U 50 50 5 0 W
ENDDRAW
ENDDEF
#
# 74157-74xx_IEEE
#
DEF 74157-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 300 400 50 H V C CNN
F1 "74157-74xx_IEEE" 250 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 100 60 0 0 0 MUX Normal 0 C C
S -250 -400 250 -600 0 0 0 N
S -250 -200 250 -400 0 0 0 N
S -250 0 250 -200 0 0 0 N
S -250 200 250 0 0 0 0 N
P 9 0 0 0 -200 200 -200 250 -250 250 -250 500 250 500 250 250 200 250 200 200 200 200 N
X VCC 16 150 500 0 D 50 50 0 0 W N
X GND 8 0 500 0 D 50 50 0 0 W N
X A/B 1 -550 300 300 R 50 50 1 1 I
X I1d 10 -550 -550 300 R 50 50 1 1 I
X I0d 11 -550 -450 300 R 50 50 1 1 I
X Qc 12 550 -300 300 L 50 50 1 1 O
X I1c 13 -550 -350 300 R 50 50 1 1 I
X I0c 14 -550 -250 300 R 50 50 1 1 I
X ~EN 15 -550 400 300 R 50 50 1 1 I I
X I0a 2 -550 150 300 R 50 50 1 1 I
X I1a 3 -550 50 300 R 50 50 1 1 I
X Qa 4 550 100 300 L 50 50 1 1 O
X I0b 5 -550 -50 300 R 50 50 1 1 I
X I1b 6 -550 -150 300 R 50 50 1 1 I
X Qb 7 550 -100 300 L 50 50 1 1 O
X Qd 9 550 -500 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# 74164-74xx_IEEE
#
DEF 74164-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 350 250 50 H V C CNN
F1 "74164-74xx_IEEE" 250 -900 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 -170 -40 60 0 0 0 & Normal 0 C C
S -250 -750 250 -850 0 1 0 N
S -250 -650 250 -750 0 1 0 N
S -250 -550 250 -650 0 1 0 N
S -250 -450 250 -550 0 1 0 N
S -250 -350 250 -450 0 1 0 N
S -250 -250 250 -350 0 1 0 N
S -250 -150 250 -250 0 1 0 N
S -250 50 250 -150 0 1 0 N
P 3 0 1 0 -100 50 -100 -150 -100 -150 N
P 9 0 1 0 -200 50 -200 100 -250 100 -250 350 250 350 250 100 200 100 200 50 200 50 N
X A 1 -550 0 300 R 50 50 1 1 I
X Qe 10 550 -500 300 L 50 50 1 1 O
X Qf 11 550 -600 300 L 50 50 1 1 O
X Qg 12 550 -700 300 L 50 50 1 1 O
X Qh 13 550 -800 300 L 50 50 1 1 O
X Vdd 14 200 350 0 D 50 50 1 1 W N
X B 2 -550 -100 300 R 50 50 1 1 I
X Qa 3 550 -50 300 L 50 50 1 1 O
X Qb 4 550 -200 300 L 50 50 1 1 O
X Qc 5 550 -300 300 L 50 50 1 1 O
X Qd 6 550 -400 300 L 50 50 1 1 O
X Vss 7 0 350 0 D 50 50 1 1 W N
X CK 8 -550 150 300 R 50 50 1 1 I C
X ~R 9 -550 250 300 R 50 50 1 1 I I
ENDDRAW
ENDDEF
#
# 74251-74xx_IEEE
#
DEF 74251-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 300 600 50 H V C CNN
F1 "74251-74xx_IEEE" 350 -800 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 250 50 0 0 0 MUX Normal 0 C C
S -250 650 250 -700 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 380 20 380 50 320 80 380 80 380 N
X VCC 16 0 650 0 D 50 50 0 0 W N
X GND 8 0 -700 0 U 50 50 0 0 W N
X I3 1 -550 -200 300 R 50 50 1 1 I
X S1 10 -550 350 300 R 50 50 1 1 I
X S0 11 -550 450 300 R 50 50 1 1 I
X I7 12 -550 -600 300 R 50 50 1 1 I
X I6 13 -550 -500 300 R 50 50 1 1 I
X I5 14 -550 -400 300 R 50 50 1 1 I
X I4 15 -550 -300 300 R 50 50 1 1 I
X I2 2 -550 -100 300 R 50 50 1 1 I
X I1 3 -550 0 300 R 50 50 1 1 I
X I0 4 -550 100 300 R 50 50 1 1 I
X Q 5 550 350 300 L 50 50 1 1 T
X ~Q 6 550 -350 300 L 50 50 1 1 T I
X ~E 7 -550 550 300 R 50 50 1 1 I I
X S2 9 -550 250 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# 74253-74xx_IEEE
#
DEF 74253-74xx_IEEE U 0 30 Y Y 1 F N
F0 "U" 300 650 50 H V C CNN
F1 "74253-74xx_IEEE" 150 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 300 60 0 0 0 MUX Normal 0 C C
S -250 -100 250 -600 0 0 0 N
S -250 450 250 -100 0 0 0 N
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
P 5 0 0 0 80 180 20 180 50 120 80 180 80 180 N
P 9 0 0 0 -200 450 -200 500 -250 500 -250 750 250 750 250 500 200 500 200 450 200 450 N
X VCC 16 150 750 0 D 50 50 0 0 W N
X GND 8 0 750 0 D 50 50 0 0 W N
X ~ENa 1 -550 350 300 R 50 50 1 1 I I
X I0b 10 -550 -250 300 R 50 50 1 1 I
X I1b 11 -550 -350 300 R 50 50 1 1 I
X I2b 12 -550 -450 300 R 50 50 1 1 I
X I3b 13 -550 -550 300 R 50 50 1 1 I
X A 14 -550 650 300 R 50 50 1 1 I
X ~ENb 15 -550 -150 300 R 50 50 1 1 I I
X B 2 -550 550 300 R 50 50 1 1 I
X I3a 3 -550 -50 300 R 50 50 1 1 I
X I2a 4 -550 50 300 R 50 50 1 1 I
X I1a 5 -550 150 300 R 50 50 1 1 I
X I0a 6 -550 250 300 R 50 50 1 1 I
X Qa 7 550 150 300 L 50 50 1 1 T
X Qb 9 550 -350 300 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# D_ALT-Device
#
DEF D_ALT-Device D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D_ALT-Device" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 50 -50 -50 N
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 F
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Q_NPN_BCE-Device
#
DEF Q_NPN_BCE-Device Q 0 0 Y N 1 F N
F0 "Q" 200 50 50 H V L CNN
F1 "Q_NPN_BCE-Device" 200 -50 50 H V L CNN
F2 "" 200 100 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 225 R 50 50 1 1 I
X C 2 100 200 100 D 50 50 1 1 P
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# R-Device
#
DEF R-Device R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R-Device" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

10112
kicad_pcb/ttl-fpga.kicad_pcb Normal file

File diff suppressed because it is too large Load Diff

241
kicad_pcb/ttl-fpga.pro Normal file
View File

@ -0,0 +1,241 @@
update=Tue 11 Jun 2019 09:23:50 PM CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=ttl-fpga.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.3
ViaDiameter1=0.6
ViaDrill1=0.3
ViaDiameter2=0.8
ViaDrill2=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

609
kicad_pcb/ttl-fpga.sch Normal file
View File

@ -0,0 +1,609 @@
EESchema Schematic File Version 4
LIBS:ttl-fpga-cache
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 3
Title "DISCRETE TTL FPGA"
Date "2019-05-31"
Rev "02L"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "PCB"
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
8000 3350 7900 3350
Wire Wire Line
7900 3350 7900 3250
$Comp
L power:VCC #PWR04
U 1 1 5FF9C392
P 7900 3250
F 0 "#PWR04" H 7900 3100 50 0001 C CNN
F 1 "VCC" H 7917 3423 50 0000 C CNN
F 2 "" H 7900 3250 50 0001 C CNN
F 3 "" H 7900 3250 50 0001 C CNN
1 7900 3250
-1 0 0 -1
$EndComp
$Comp
L power:GNDD #PWR06
U 1 1 5FF9C39C
P 7800 3450
F 0 "#PWR06" H 7800 3200 50 0001 C CNN
F 1 "GNDD" V 7804 3340 50 0000 R CNN
F 2 "" H 7800 3450 50 0001 C CNN
F 3 "" H 7800 3450 50 0001 C CNN
1 7800 3450
0 1 -1 0
$EndComp
Wire Wire Line
7800 3450 8000 3450
Wire Wire Line
7200 3750 7200 3300
Wire Wire Line
8000 3750 7200 3750
Wire Wire Line
7300 3650 7300 3100
Wire Wire Line
8000 3650 7300 3650
Wire Wire Line
7400 3550 7400 3000
Wire Wire Line
8000 3550 7400 3550
Text Label 7550 4150 0 50 ~ 0
fabric_r3
Text Label 7550 4250 0 50 ~ 0
fabric_r2
Text Label 7550 4350 0 50 ~ 0
fabric_r1
Text Label 7550 4450 0 50 ~ 0
fabric_r0
Wire Wire Line
8000 4350 7550 4350
Wire Wire Line
8000 4250 7550 4250
Wire Wire Line
8000 4150 7550 4150
Entry Wire Line
7550 4350 7450 4450
Entry Wire Line
7550 4250 7450 4350
Entry Wire Line
7550 4150 7450 4250
Entry Wire Line
7550 4450 7450 4550
Wire Bus Line
7450 4550 6800 4550
Wire Wire Line
4450 3300 4450 3250
Wire Wire Line
5000 3250 5000 3300
Wire Wire Line
5000 3300 5650 3300
Wire Wire Line
4450 3250 5000 3250
Connection ~ 4450 3300
Wire Wire Line
4450 3300 4550 3300
Wire Wire Line
4450 3100 4450 3050
Wire Wire Line
4450 3050 5000 3050
Wire Wire Line
5000 3050 5000 3100
Wire Wire Line
5000 3100 5550 3100
Connection ~ 4450 3100
Wire Wire Line
4450 3100 4550 3100
Wire Wire Line
4950 3000 4950 2950
Wire Wire Line
4950 2950 4450 2950
Wire Wire Line
4950 3000 5450 3000
Wire Wire Line
4450 3000 4550 3000
Wire Wire Line
4450 2950 4450 3000
Connection ~ 4450 3000
Wire Wire Line
4200 3400 4300 3400
Wire Wire Line
3900 3000 4450 3000
Wire Wire Line
4000 3100 4450 3100
Wire Wire Line
4100 3300 4450 3300
Entry Wire Line
3900 4250 3800 4150
Entry Wire Line
3900 4550 3800 4450
Entry Wire Line
3900 4450 3800 4350
Entry Wire Line
3900 4350 3800 4250
Wire Wire Line
3350 4150 3800 4150
Wire Wire Line
3350 4250 3800 4250
Wire Wire Line
3350 4350 3800 4350
Wire Wire Line
3350 4450 3800 4450
Text Label 3800 4450 2 50 ~ 0
fabric_l0
Text Label 3800 4350 2 50 ~ 0
fabric_l1
Text Label 3800 4250 2 50 ~ 0
fabric_l2
Text Label 3800 4150 2 50 ~ 0
fabric_l3
Wire Wire Line
3350 3550 3900 3550
Wire Wire Line
3900 3550 3900 3000
Wire Wire Line
3350 3650 4000 3650
Wire Wire Line
4000 3650 4000 3100
Wire Wire Line
3350 3750 4100 3750
Wire Wire Line
4100 3750 4100 3300
Wire Wire Line
3350 3850 4200 3850
Wire Wire Line
4200 3850 4200 3400
Wire Wire Line
3550 3450 3350 3450
$Comp
L power:GNDD #PWR05
U 1 1 5FE8BD0F
P 3550 3450
F 0 "#PWR05" H 3550 3200 50 0001 C CNN
F 1 "GNDD" V 3554 3340 50 0000 R CNN
F 2 "" H 3550 3450 50 0001 C CNN
F 3 "" H 3550 3450 50 0001 C CNN
1 3550 3450
0 -1 -1 0
$EndComp
$Comp
L power:VCC #PWR03
U 1 1 5FE8B843
P 3450 3250
F 0 "#PWR03" H 3450 3100 50 0001 C CNN
F 1 "VCC" H 3467 3423 50 0000 C CNN
F 2 "" H 3450 3250 50 0001 C CNN
F 3 "" H 3450 3250 50 0001 C CNN
1 3450 3250
1 0 0 -1
$EndComp
Wire Wire Line
3450 3350 3450 3250
Wire Wire Line
3350 3350 3450 3350
Wire Wire Line
6800 3400 7100 3400
Text Label 3950 4550 0 50 ~ 0
fabric_l[3..0]
Wire Wire Line
7100 3400 7100 3850
Wire Wire Line
7100 3850 8000 3850
Wire Wire Line
3350 3950 8000 3950
Text Notes 3100 4500 2 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI\nMISO\nMOSI_D\nI3\nI2\nI1\nI0
Text Notes 8250 4500 0 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nmiso\nmosi\n\nI3\nI2\nI1\nI0
Wire Wire Line
5250 5600 5250 5550
$Comp
L power:VCC #PWR012
U 1 1 60046AFF
P 5250 5550
F 0 "#PWR012" H 5250 5400 50 0001 C CNN
F 1 "VCC" H 5150 5650 50 0000 C CNN
F 2 "" H 5250 5550 50 0001 C CNN
F 3 "" H 5250 5550 50 0001 C CNN
1 5250 5550
1 0 0 -1
$EndComp
$Comp
L power:GNDD #PWR09
U 1 1 60046AF5
P 5200 5200
F 0 "#PWR09" H 5200 4950 50 0001 C CNN
F 1 "GNDD" H 5204 5045 50 0000 C CNN
F 2 "" H 5200 5200 50 0001 C CNN
F 3 "" H 5200 5200 50 0001 C CNN
1 5200 5200
1 0 0 -1
$EndComp
Wire Wire Line
5200 5150 5350 5150
Wire Wire Line
5350 5150 5350 5600
Text Label 6050 5150 3 50 ~ 0
fabric_b3
Text Label 6150 5150 3 50 ~ 0
fabric_b2
Text Label 6250 5150 3 50 ~ 0
fabric_b1
Text Label 6350 5150 3 50 ~ 0
fabric_b0
Wire Wire Line
6350 5600 6350 5150
Wire Wire Line
6250 5600 6250 5150
Wire Wire Line
6150 5600 6150 5150
Wire Wire Line
6050 5600 6050 5150
Entry Wire Line
6250 5150 6350 5050
Entry Wire Line
6150 5150 6250 5050
Entry Wire Line
6050 5150 6150 5050
Entry Wire Line
6350 5150 6450 5050
$Sheet
S 4550 2700 2250 2250
U 5D77FDBE
F0 "LogicBlock" 50
F1 "logic_block.sch" 50
F2 "fabric_b[3..0]" I R 6800 4850 50
F3 "fabric_t[3..0]" I R 6800 2800 50
F4 "fabric_l[3..0]" I L 4550 4550 50
F5 "fabric_r[3..0]" I R 6800 4550 50
F6 "rst_n" I L 4550 3100 50
F7 "clk" I L 4550 3000 50
F8 "isp_mosi" I L 4550 3400 50
F9 "isp_sck" I L 4550 3300 50
F10 "isp_miso" O R 6800 3400 50
$EndSheet
Wire Bus Line
6800 4850 6900 4850
Wire Bus Line
6900 4850 6900 5050
Wire Wire Line
5450 5600 5450 3000
Connection ~ 5450 3000
Wire Wire Line
5450 3000 7400 3000
Wire Wire Line
5550 5600 5550 3100
Connection ~ 5550 3100
Wire Wire Line
5550 3100 7300 3100
Wire Wire Line
5650 5600 5650 3300
Connection ~ 5650 3300
Wire Bus Line
3900 4550 4550 4550
Wire Wire Line
5750 4050 5750 5600
Wire Wire Line
3350 4050 5750 4050
Text Notes 6400 5850 3 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI3\nI2\nI1\nI0
$Comp
L Connector:Conn_01x12_Female J4
U 1 1 60090C3D
P 5750 5800
F 0 "J4" H 5700 6400 50 0000 C CNN
F 1 "Bottom" V 5650 5050 50 0000 C CNN
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 5750 5800 50 0001 C CNN
F 3 "~" H 5750 5800 50 0001 C CNN
1 5750 5800
0 -1 1 0
$EndComp
Text Notes 6400 1800 1 63 ~ 0
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI3\nI2\nI1\nI0
$Comp
L power:VCC #PWR01
U 1 1 600A7963
P 5150 2150
F 0 "#PWR01" H 5150 2000 50 0001 C CNN
F 1 "VCC" H 5250 2200 50 0000 C CNN
F 2 "" H 5150 2150 50 0001 C CNN
F 3 "" H 5150 2150 50 0001 C CNN
1 5150 2150
-1 0 0 -1
$EndComp
Wire Wire Line
5250 2250 5150 2250
Wire Wire Line
5250 2050 5250 2250
Text Label 6050 2500 1 50 ~ 0
fabric_t3
Text Label 6150 2500 1 50 ~ 0
fabric_t2
Text Label 6250 2500 1 50 ~ 0
fabric_t1
Text Label 6350 2500 1 50 ~ 0
fabric_t0
Wire Wire Line
6350 2050 6350 2500
Wire Wire Line
6250 2050 6250 2500
Wire Wire Line
6150 2050 6150 2500
Wire Wire Line
6050 2050 6050 2500
Entry Wire Line
6250 2500 6350 2600
Entry Wire Line
6150 2500 6250 2600
Entry Wire Line
6050 2500 6150 2600
Entry Wire Line
6350 2500 6450 2600
Wire Bus Line
6900 2800 6800 2800
Wire Bus Line
6900 2600 6900 2800
Text Label 6250 5050 0 50 ~ 0
fabric_b[3..0]
Text Label 6450 2600 0 50 ~ 0
fabric_t[3..0]
Wire Wire Line
5450 2050 5450 3000
Wire Wire Line
5550 3100 5550 2050
Wire Wire Line
5650 3300 7200 3300
Wire Wire Line
5650 3300 5650 2050
Wire Notes Line
6400 3400 4950 3400
Wire Notes Line
6400 3400 6300 3350
Wire Notes Line
6400 3400 6300 3450
Text Label 6900 4550 0 50 ~ 0
fabric_r[3..0]
Wire Wire Line
5750 2050 5750 2500
Wire Wire Line
5750 2500 4300 2500
Wire Wire Line
4300 2500 4300 3400
Connection ~ 4300 3400
Wire Wire Line
4300 3400 4550 3400
Wire Notes Line
8550 3850 8650 3850
Wire Notes Line
8550 3950 8600 3900
Wire Notes Line
8550 3950 8600 4000
Wire Notes Line
8650 3950 8550 3950
Wire Notes Line
8650 3850 8650 3950
Wire Notes Line
2850 3950 2600 3950
Wire Notes Line
2600 3950 2600 4050
Wire Notes Line
2600 4050 2700 4050
Wire Notes Line
2650 4000 2700 4050
Wire Notes Line
2700 4050 2650 4100
Wire Notes Line
2450 3850 2850 3850
Wire Notes Line
2850 3850 2800 3800
Wire Notes Line
2850 3850 2800 3900
Wire Notes Line
5750 6200 5750 6350
Wire Notes Line
5750 6350 5700 6300
Wire Notes Line
5750 6350 5800 6300
Wire Notes Line
5750 1300 5750 1450
Wire Notes Line
5750 1450 5700 1400
Wire Notes Line
5750 1450 5800 1400
Text Notes 1900 3850 0 50 ~ 0
PROGRAMMER
Wire Notes Line
2850 3750 2450 3750
Wire Notes Line
2850 3750 2800 3700
Wire Notes Line
2850 3750 2800 3800
Wire Notes Line
2450 3650 2450 3950
Wire Notes Line
2450 3950 1850 3950
Wire Notes Line
1850 3950 1850 3650
Wire Notes Line
1850 3650 2450 3650
Wire Wire Line
5850 5600 5850 2050
Wire Wire Line
5350 2250 5350 2050
$Comp
L power:GNDD #PWR02
U 1 1 600A7959
P 5350 2250
F 0 "#PWR02" H 5350 2000 50 0001 C CNN
F 1 "GNDD" H 5354 2095 50 0000 C CNN
F 2 "" H 5350 2250 50 0001 C CNN
F 3 "" H 5350 2250 50 0001 C CNN
1 5350 2250
-1 0 0 -1
$EndComp
Wire Wire Line
5150 2250 5150 2150
Wire Wire Line
5200 5150 5200 5200
NoConn ~ 5950 2050
NoConn ~ 8000 4050
NoConn ~ 5950 5600
Wire Notes Line
3150 1850 8200 1850
Wire Notes Line
8200 1850 8200 5800
Wire Notes Line
8200 5800 3150 5800
Wire Notes Line
3150 5800 3150 1850
$Comp
L Connector:Conn_01x12_Male J1
U 1 1 5CF30EFB
P 5750 1850
F 0 "J1" H 5850 2450 50 0000 R CNN
F 1 "Top" V 5850 1200 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 5750 1850 50 0001 C CNN
F 3 "~" H 5750 1850 50 0001 C CNN
1 5750 1850
0 -1 1 0
$EndComp
$Comp
L Connector:Conn_01x12_Male J3
U 1 1 5CF23FEF
P 8200 3850
F 0 "J3" H 8300 4450 50 0000 R CNN
F 1 "Right" H 8400 3200 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 8200 3850 50 0001 C CNN
F 3 "~" H 8200 3850 50 0001 C CNN
1 8200 3850
-1 0 0 -1
$EndComp
$Comp
L Connector:Conn_01x12_Female J2
U 1 1 5FE88CA2
P 3150 3850
F 0 "J2" H 3100 4450 50 0000 C CNN
F 1 "Left" H 3050 3200 50 0000 C CNN
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 3150 3850 50 0001 C CNN
F 3 "~" H 3150 3850 50 0001 C CNN
1 3150 3850
-1 0 0 -1
$EndComp
$Comp
L Device:CP C1
U 1 1 5CF70F0E
P 3550 5150
F 0 "C1" H 3668 5196 50 0000 L CNN
F 1 "10u" H 3668 5105 50 0000 L CNN
F 2 "Capacitor_SMD:C_1206_3216Metric" H 3588 5000 50 0001 C CNN
F 3 "~" H 3550 5150 50 0001 C CNN
1 3550 5150
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR07
U 1 1 5CF715DB
P 3550 4900
F 0 "#PWR07" H 3550 4750 50 0001 C CNN
F 1 "VCC" H 3567 5073 50 0000 C CNN
F 2 "" H 3550 4900 50 0001 C CNN
F 3 "" H 3550 4900 50 0001 C CNN
1 3550 4900
1 0 0 -1
$EndComp
Wire Wire Line
3550 5000 3550 4900
$Comp
L Device:LED D?
U 1 1 5CFB92E6
P 4150 5200
AR Path="/5D77FDBE/5D7AF013/5CFB92E6" Ref="D?" Part="1"
AR Path="/5D77FDBE/5CFB92E6" Ref="D?" Part="1"
AR Path="/5CFB92E6" Ref="D1" Part="1"
F 0 "D1" V 4200 5100 50 0000 R CNN
F 1 "PWR" V 4100 5100 50 0000 R CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 4150 5200 50 0001 C CNN
F 3 "~" H 4150 5200 50 0001 C CNN
1 4150 5200
0 -1 -1 0
$EndComp
$Comp
L Device:R R?
U 1 1 5CFB92EC
P 3950 5000
AR Path="/5D77FDBE/5D7AF013/5CFB92EC" Ref="R?" Part="1"
AR Path="/5D77FDBE/5CFB92EC" Ref="R?" Part="1"
AR Path="/5CFB92EC" Ref="R1" Part="1"
F 0 "R1" H 4020 5046 50 0000 L CNN
F 1 "470" H 4020 4955 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 3880 5000 50 0001 C CNN
F 3 "~" H 3950 5000 50 0001 C CNN
1 3950 5000
0 -1 -1 0
$EndComp
$Comp
L power:VCC #PWR08
U 1 1 5CFBED78
P 3750 4900
F 0 "#PWR08" H 3750 4750 50 0001 C CNN
F 1 "VCC" H 3767 5073 50 0000 C CNN
F 2 "" H 3750 4900 50 0001 C CNN
F 3 "" H 3750 4900 50 0001 C CNN
1 3750 4900
1 0 0 -1
$EndComp
Wire Wire Line
3800 5000 3750 5000
Wire Wire Line
3750 5000 3750 4900
Wire Wire Line
4100 5000 4150 5000
Wire Wire Line
4150 5000 4150 5050
Wire Wire Line
3550 5400 3550 5300
$Comp
L power:GNDD #PWR010
U 1 1 5CF71B50
P 3550 5400
F 0 "#PWR010" H 3550 5150 50 0001 C CNN
F 1 "GNDD" V 3554 5290 50 0000 R CNN
F 2 "" H 3550 5400 50 0001 C CNN
F 3 "" H 3550 5400 50 0001 C CNN
1 3550 5400
1 0 0 -1
$EndComp
Wire Wire Line
4150 5350 4150 5400
$Comp
L power:GNDD #PWR011
U 1 1 5CFBCC03
P 4150 5400
F 0 "#PWR011" H 4150 5150 50 0001 C CNN
F 1 "GNDD" V 4154 5290 50 0000 R CNN
F 2 "" H 4150 5400 50 0001 C CNN
F 3 "" H 4150 5400 50 0001 C CNN
1 4150 5400
1 0 0 -1
$EndComp
Wire Wire Line
8000 4450 7550 4450
Text Label 3450 4050 0 50 ~ 0
mosi_d
Text Label 3450 3950 0 50 ~ 0
miso
Wire Bus Line
7450 4250 7450 4550
Wire Bus Line
3900 4250 3900 4550
Wire Bus Line
6150 2600 6900 2600
Wire Bus Line
6150 5050 6900 5050
$EndSCHEMATC

5
sw/kousaten/.gitignore vendored Normal file
View File

@ -0,0 +1,5 @@
*.user
*~
Makefile
*.autosave
build-*

View File

@ -0,0 +1,8 @@
cmake_minimum_required(VERSION 2.8)
project(kousaten)
#set(CMAKE_BUILD_TYPE Release)
set(CMAKE_C_FLAGS "-Wall")
aux_source_directory(./src SRC_LIST)
add_executable(${PROJECT_NAME} ${SRC_LIST})

2
sw/kousaten/README.MD Normal file
View File

@ -0,0 +1,2 @@
# TTL-FPGA Compiler *Kousaten*
Tool to generate bitstreams for the TTL-FPGA after manual synthesis and PNR.

View File

@ -0,0 +1,4 @@
PLLLL]
[LLLL]
[LLLL]
[LLLL

View File

@ -0,0 +1 @@
PL

View File

@ -0,0 +1,9 @@
#!/bin/bash
if [ $# -lt 2 ]; then
echo "Usage: $0 </dev/ttyX> <progfile>"
exit 1
fi
stty -F "$1" raw
cat "$2" > "$1"

56
sw/kousaten/src/fpga.c Normal file
View File

@ -0,0 +1,56 @@
#include "fpga.h"
#include "fpga_global.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
int fpga_generate_bitstream(struct fpga_chain *chain,
char *filename, int ascii)
{
int i;
char *buf = NULL;
FILE *bitstream = stdout;
if (strcmp(filename, "-")) {
bitstream = fopen(filename, "wb");
}
if (!bitstream) {
report(LL_ERROR,
"Could not open output file '%s'.",
filename);
errno = EIO;
goto fail;
}
report(LL_INFO, "Generating bitstream...");
for (i = chain->length - 1; i >= 0; --i) {
report(LL_DEBUG,
"Generating bitstream for cell %p (%c)...",
chain->head[i], chain->head[i]->type->identifier);
buf = chain->head[i]->type->isp_generate_bitstream(chain->head[i]);
if (!buf) {
report(LL_ERROR,
"Error during bitstream generation for cell %p.",
chain->head[i]);
errno = ETYPE;
goto fail;
}
for (int j = 0; j < chain->head[i]->type->isp_length; ++j) {
if (ascii)
fprintf(bitstream, "%02X ", buf[j] & 0xFF);
else
fputc(buf[j] & 0xFF, bitstream);
}
if (ascii)
fprintf(bitstream, "\n");
free(buf);
}
return 0;
fail:
if (bitstream && (strcmp(filename, "-")))
fclose(bitstream);
return 1;
}

8
sw/kousaten/src/fpga.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef FPGA_H
#define FPGA_H
#include "fpga_cell.h"
int fpga_generate_bitstream(struct fpga_chain *chain,
char *filename, int ascii);
#endif // FPGA_H

329
sw/kousaten/src/fpga_cell.c Normal file
View File

@ -0,0 +1,329 @@
#include "fpga_cell.h"
#include "fpga_global.h"
#include "fpga_cell_lut34.h"
#include "fpga_cell_none.h"
#include "fpga_cell_wire.h"
#include <stdlib.h>
static struct fpga_cell_type fpga_cell_list[] = {
{
.identifier = ' ',
.cell_new = fpga_cell_none_new,
.get_next_isp = fpga_cell_none_get_next_isp,
.isp_length = 0,
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
},
{
.identifier = '[',
.cell_new = fpga_cell_wire_new,
.get_next_isp = fpga_cell_wire_get_next_isp,
.isp_length = 0,
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
},
{
.identifier = ']',
.cell_new = fpga_cell_wire_new,
.get_next_isp = fpga_cell_wire_get_next_isp,
.isp_length = 0,
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
},
{
.identifier = 'P',
.cell_new = fpga_cell_wire_new,
.get_next_isp = fpga_cell_wire_get_next_isp,
.isp_length = 0,
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
},
{
.identifier = 'L',
.cell_new = fpga_cell_lut34_new,
.get_next_isp = fpga_cell_lut34_get_next_isp,
.isp_length = 6,
.isp_generate_bitstream = fpga_cell_lut34_isp_generate_bitstream
},
{
.identifier = '\0',
.cell_new = NULL,
.get_next_isp = NULL,
.isp_length = 0,
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
}
};
void fpga_cell_init(struct fpga_cell *cell,
struct fpga_cell_type *cell_type)
{
int i;
for (i = 0; i < FPGA_CELL_CONNECTION_COUNT; ++i) {
cell->cell_connections[i] = NULL;
}
cell->type = cell_type;
//fpga_cell->get_next_isp = fpga_cell_get_next_isp_dummy;
report(LL_DEBUG,
"Initialized cell of type %d at %p.",
cell_type, cell);
}
enum fpga_cell_position fpga_cell_connection_opposing(enum fpga_cell_position position)
{
switch (position) {
case LEFT:
return RIGHT;
case RIGHT:
return LEFT;
case TOP:
return BOTTOM;
case BOTTOM:
return TOP;
default:
report(LL_ERROR,
"Internal error: Requested opposite of invalid position %d.",
position);
return LEFT;
}
}
/**
* @brief fpga_cell_connect Connect <fpga_cell> to the <position> of <target_cell>
* @param fpga_cell
* @param target_cell
* @param position
* @return 0 on success, -1 on failure
*/
int fpga_cell_connect(struct fpga_cell *fpga_cell,
struct fpga_cell *target_cell,
enum fpga_cell_position position)
{
if (target_cell->cell_connections[position] ||
fpga_cell->cell_connections[fpga_cell_connection_opposing(position)]) {
report(LL_WARNING,
"Tried to connect cell %p to pos %d of %p, even though a connection already exists for a least one of them.",
fpga_cell, target_cell, position);
errno = -ECONN;
return -1;
}
target_cell->cell_connections[position] = fpga_cell;
fpga_cell->cell_connections[fpga_cell_connection_opposing(position)] = target_cell;
report(LL_DEBUG,
"Connected cell %p to port %d of %p.",
fpga_cell, position, target_cell);
return 0;
}
/**
* @brief fpga_cell_get_far Get cell on the far <position> of <cell>
* @param cell
* @param position
* @return
*/
struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell,
enum fpga_cell_position position)
{
struct fpga_cell *next = cell;
while (next->cell_connections[position]) {
next = next->cell_connections[position];
}
return next;
}
/**
* @brief fpga_cell_get_next_isp Get the next cell in the ISP chain
* @param fpga_cell the current cell in the ISP chain
* @param isp_channel the current channel. This will be updated when calling this function!
* @return the next ISP cell
*/
struct fpga_cell *fpga_cell_get_next_isp_dummy(struct fpga_cell *cell,
enum fpga_isp_channel *isp_channel)
{
report(LL_CRITICAL,
"Internal error. Cell type %c does not implement get_next_isp!",
cell->type->identifier);
*isp_channel = FPGA_ISP_CHANNEL_ERROR;
return NULL;
}
/**
* @brief isp_generate_bitstream_dummy
* @param cell
* @param buf
* @return
*/
char *fpga_cell_isp_generate_bitstream_dummy(struct fpga_cell *cell)
{
report(LL_CRITICAL,
"Internal error. Cell type %c does not implement isp_generate_bitstream!",
cell->type->identifier);
return NULL;
}
/**
* @brief fpga_cell_new Create a new instance of type <identifier>
* @param identifier
* @return
*/
struct fpga_cell *fpga_cell_new(char identifier)
{
struct fpga_cell_type *cell_type = fpga_cell_list;
struct fpga_cell *cell = NULL;
while (cell_type->identifier) {
if (identifier == cell_type->identifier) {
cell = cell_type->cell_new();
if (!cell) {
report(LL_CRITICAL,
"Out of memory when creating cell.");
return NULL;
}
cell->type = cell_type;
report(LL_DEBUG,
"Created cell %p of type %c.",
cell, identifier);
return cell;
}
cell_type++;
}
report(LL_ERROR,
"Invalid cell type %c found in FDEF.",
identifier);
return NULL;
}
/**
* @brief fpga_isp_chain_new
* @param entry
* @return
*/
struct fpga_chain *fpga_isp_chain_new(struct fpga_cell *entry)
{
struct fpga_cell *current_cell = entry;
enum fpga_isp_channel current_channel = FPGA_ISP_CHANNEL_NORMAL;
struct fpga_chain *chain;
report(LL_INFO,
"Generating ISP chain...");
if (entry->type->identifier != 'P') {
report(LL_CRITICAL,
"Entry cell must be of type P, was '%c'",
entry->type->identifier);
errno = EINVAL;
return NULL;
}
chain = calloc(sizeof (struct fpga_chain), 1);
if (!chain) {
report (LL_CRITICAL,
"Out of memory during ISP chain generation.");
errno = ENOMEM;
return NULL;
}
while (current_cell) {
if (current_channel == FPGA_ISP_CHANNEL_NORMAL &&
current_cell->type->isp_length > 0) {
report(LL_DEBUG,
"Adding %p (%c) to ISP chain.",
current_cell, current_cell->type->identifier);
if (!chain->head) {
chain->head = malloc(sizeof(chain->head));
*(chain->head) = current_cell;
chain->length = 1;
} else {
chain->length++;
chain->head = realloc(chain->head,
sizeof(chain->head) * chain->length);
*(chain->head + chain->length - 1) = current_cell;
}
} else {
report(LL_DEBUG,
"Using %p (%c) for ISP routing.",
current_cell, current_cell->type->identifier);
}
current_cell = current_cell->type->get_next_isp(current_cell,
&current_channel);
if (current_channel == FPGA_ISP_CHANNEL_ERROR) {
/* TODO: Clean up memory */
errno = ETYPE;
return NULL;
}
}
report(LL_INFO,
"Added %d cells to ISP chain.",
chain->length);
for (int i = 0; i < chain->length; ++i) {
report(LL_DEBUG,
" %4d = %p",
i, chain->head[i]);
}
report(LL_INFO,
"ISP chain generation finished.");
return chain;
}
int fpga_cell_bitstream_set_bit(char *buffer, char *sbuffer,
int bit, int value) {
int byteno;
int bitno;
bit = 47 - bit;
bitno = 7 - (bit % 8);
byteno = bit / 8;
value = !!value; /* Make sure it's a proper boolean value */
if ((sbuffer[byteno] & (1 << bitno))) { /* Already set */
return value == !((buffer[byteno] & (1 << bitno)));
} else {
sbuffer[byteno] |= (1 << bitno);
if (value)
buffer[byteno] |= (1 << bitno);
else
buffer[byteno] &= ~(1 << bitno);
}
return 0;
}
int fpga_cell_bitstream_set_bits(char *buffer, char *sbuffer,
int value, int nbits, int *mapping)
{
int i;
int ret = 0;
for (i = 0; i < nbits; ++i) {
ret = ret || fpga_cell_bitstream_set_bit(buffer, sbuffer,
mapping[i], value & (1 << i));
}
return ret;
}
int fpga_cell_bitstream_is_set(char *buffer, int bit)
{
int byteno;
int bitno;
bit = 47 - bit;
bitno = 7 - (bit % 8);
byteno = bit / 8;
return !!(buffer[byteno] & (1 << bitno));
}

View File

@ -0,0 +1,67 @@
#ifndef FPGA_CELL_H
#define FPGA_CELL_H
#include <stddef.h>
enum fpga_cell_position {
LEFT = 0,
TOP,
RIGHT,
BOTTOM,
FPGA_CELL_CONNECTION_COUNT
};
enum fpga_isp_channel {
FPGA_ISP_CHANNEL_NORMAL = 0,
FPGA_ISP_CHANNEL_BACK,
FPGA_ISP_CHANNEL_LFDN,
FPGA_ISP_CHANNEL_DNUP,
FPGA_ISP_CHANNEL_ERROR
};
struct fpga_cell_type
{
char identifier;
struct fpga_cell *(*cell_new)();
struct fpga_cell *(*get_next_isp)(struct fpga_cell *cell,
enum fpga_isp_channel *isp_channel);
unsigned long isp_length;
char *(*isp_generate_bitstream)(struct fpga_cell *cell);
};
/* FPGA Logic cell base parameters */
struct fpga_cell
{
struct fpga_cell_type *type;
struct fpga_cell *cell_connections[FPGA_CELL_CONNECTION_COUNT];
/* Cell-specific data will be appended depending on the cell type. */
};
struct fpga_chain {
struct fpga_cell **head;
int length;
};
void fpga_cell_init(struct fpga_cell *cell,
struct fpga_cell_type *cell_type);
int fpga_cell_connect(struct fpga_cell *fpga_cell,
struct fpga_cell *target_cell,
enum fpga_cell_position position);
struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell,
enum fpga_cell_position position);
struct fpga_cell *fpga_cell_get_next_isp_dummy(struct fpga_cell *fpga_cell,
enum fpga_isp_channel *isp_channel);
char *fpga_cell_isp_generate_bitstream_dummy(struct fpga_cell *cell);
struct fpga_cell *fpga_cell_new(char identifier);
#define FPGA_TO_CELL(a) ((struct fpga_cell*) a)
struct fpga_chain *fpga_isp_chain_new(struct fpga_cell *entry);
int fpga_cell_bitstream_set_bit(char *buffer, char *sbuffer,
int bit, int value);
int fpga_cell_bitstream_set_bits(char *buffer, char *sbuffer,
int value, int nbits, int *mapping);
int fpga_cell_bitstream_is_set(char *buffer, int bit);
#endif // FPGA_CELL_H

View File

@ -0,0 +1,300 @@
#include "fpga_cell_lut34.h"
#include "fpga_global.h"
#include <stdlib.h>
#include <string.h>
#define LUTD_POSITION 16 /* First bit of LUTD cfg bits */
#define LUTD_BIT_COUNT 16 /* To be applied for any cfg no > 15 */
static int need_fix = 1;
/* LUT Definitions (correct offset, no fix must be applied) */
static int LUT4_BITMAP[16] = {
24, 25, 26, 27, 28, 29, 30, 31,
16, 17, 18, 19, 20, 21, 22, 23
};
static int LUT3_BITMAP[2][8] = {
{24, 25, 26, 27, 28, 29, 30, 31},
{16, 17, 18, 19, 20, 21, 22, 23}
};
/* LUT Config Definitions */
static int BIT_LUT_SYNC_N = 20;
static int BIT_LUT_SPLIT_N = 21;
/* LUT IN MUX Definitions */
static char LUT_IN_MUX[4][8] = {
{LUT_NET_F2, LUT_NET_L0, LUT_NET_L3, LUT_NET_L2, LUT_NET_L1, LUT_NET_F1, LUT_NET_F0, LUT_NET_T0},
{LUT_NET_F0, LUT_NET_F1, LUT_NET_L1, LUT_NET_L2, LUT_NET_L3, LUT_NET_L0, LUT_NET_F2, LUT_NET_T1},
{LUT_NET_F3, LUT_NET_L0, LUT_NET_L3, LUT_NET_L2, LUT_NET_L1, LUT_NET_F1, LUT_NET_F0, LUT_NET_T2},
{LUT_NET_F0, LUT_NET_F1, LUT_NET_L1, LUT_NET_L2, LUT_NET_L3, LUT_NET_L0, LUT_NET_F3, LUT_NET_T3}
};
static int LUT_IN_BITMAP[4][3] = {
{12, 11, 19},
{ 8, 9, 10},
{15, 14, 13},
{16, 17, 18}
};
/* LUT OUT MUX Definitions */
static int LUT_OUT_MUX[4][4] = {
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_A, LUT_OUT_A},
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
};
static int LUT_OUT_BITMAP[2][2] = {
{27, 23},
{25, 30}
};
static int LUT_OUT_EN_N_BITMAP[4] = {
22, 26, 31, 24
};
/* Routing Definitions */
static int ROUTE_BITMAP[8] = {
3, 6, 4, 0, /* Left */
5, 1, 2, 7, /* Top */
};
/* LED Definitions */
static int BIT_LED_LUT_IN = 28;
static int BIT_LED_LUT_OUT_N = 29; /* Low-active */
static inline int fpga_cell_lut34_is_driven(char drive_sel)
{
return (drive_sel != LUT_OUT_DC && drive_sel != LUT_OUT_Z);
}
static int fpga_cell_lut34_lut_get_mux(int lut, char port)
{
int i;
if (port == LUT_NET_DC)
return 0;
for (i = 0; i < 8; ++i) {
if (LUT_IN_MUX[lut][i] == port)
return i;
}
return -1;
}
static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports)
{
int i;
int lut;
if (lut_group < 0 || lut_group > 2) {
report(LL_ERROR,
"Invalid LUT group requested.");
return -1;
}
lut = lut_group * 2;
ports = ports + lut;
for (i = 0; i < 4; ++i) {
if (!fpga_cell_lut34_is_driven(ports[0]) ||
ports[0] == LUT_OUT_MUX[lut][i]) {
if (!fpga_cell_lut34_is_driven(ports[1]) ||
ports[1] == LUT_OUT_MUX[lut + 1][i])
return i;
}
}
return -1;
}
struct fpga_cell *fpga_cell_lut34_new()
{
struct fpga_cell_lut34 *fpga_cell_lut_34;
fpga_cell_lut_34 = malloc(sizeof(struct fpga_cell_lut34));
fpga_cell_lut_34->LUT3[0] = -1;
fpga_cell_lut_34->LUT3[1] = -1;
fpga_cell_lut_34->LUT4 = -1;
return FPGA_TO_CELL(fpga_cell_lut_34);
}
struct fpga_cell *fpga_cell_lut34_get_next_isp(struct fpga_cell *cell,
enum fpga_isp_channel *isp_channel)
{
switch (*isp_channel) {
case FPGA_ISP_CHANNEL_LFDN:
*isp_channel = FPGA_ISP_CHANNEL_NORMAL;
return cell->cell_connections[BOTTOM];
case FPGA_ISP_CHANNEL_NORMAL:
return cell->cell_connections[RIGHT];
case FPGA_ISP_CHANNEL_BACK:
return cell->cell_connections[LEFT];
default:
report(LL_ERROR,
"Unhandled ISP channel %d for LUT34.",
*isp_channel);
}
return NULL;
}
static void fix_bitfields(int *bitmap, int count)
{
int i;
for (i = 0; i < count; ++i) {
if (bitmap[i] >= LUTD_POSITION) {
bitmap[i] += LUTD_BIT_COUNT;
}
}
}
#define BS_SET_BIT(bitno, value, errmsg, ...)\
{if (fpga_cell_bitstream_set_bit(buf, sbuf, bitno, value)) {\
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
errno = ERECONF;\
goto fail;\
}} (void)0
#define BS_SET_BITS(value, nbits, mapping, errmsg, ...) \
{if (fpga_cell_bitstream_set_bits(buf, sbuf, value, nbits, mapping)) {\
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
errno = ERECONF;\
goto fail;\
}} (void)0
char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
{
struct fpga_cell_lut34 *lut34 = (struct fpga_cell_lut34 *) cell;
char *buf = NULL;
char *sbuf = NULL;
int i;
int temp;
buf = calloc(cell->type->isp_length, sizeof(char));
sbuf = calloc(cell->type->isp_length, sizeof(char));
if (!buf || !sbuf) {
report(LL_CRITICAL,
"Out of memory during bitstream generation.");
errno = ENOMEM;
goto fail;
}
/* Reposition cfg bits after LUTD cfg, cheap workaround to use the same
cfg names as the schematic does. */
if (need_fix) {
need_fix = 0;
for (i = 0; i < 4; ++i) {
fix_bitfields(LUT_IN_BITMAP[i], 3);
}
for (i = 0; i < 2; ++i) {
fix_bitfields(LUT_OUT_BITMAP[i], 2);
}
fix_bitfields(LUT_OUT_EN_N_BITMAP, 4);
fix_bitfields(ROUTE_BITMAP, 8);
fix_bitfields(&BIT_LED_LUT_IN, 1);
fix_bitfields(&BIT_LED_LUT_OUT_N, 1);
fix_bitfields(&BIT_LUT_SYNC_N, 1);
fix_bitfields(&BIT_LUT_SPLIT_N, 1);
}
/* LEDs */
BS_SET_BIT(BIT_LED_LUT_IN, 1,
"Couldn't set LUT in LED to %d.", 1);
BS_SET_BIT(BIT_LED_LUT_OUT_N, 0,
"Couldn't set LUT out LED to %d.", 0);
/* LUT input sel */
for (i = 0; i < 4; ++i) {
temp = fpga_cell_lut34_lut_get_mux(i, lut34->lut_in_sel[i]);
if (temp < 0) {
report(LL_ERROR,
"Invalid input mux '%c' selected for mux %d on cell %p.",
lut34->lut_in_sel[i], i, cell);
errno = EINVAL;
goto fail;
}
BS_SET_BITS(temp, 3, LUT_IN_BITMAP[i], "Couldn't set LUT input sel for input %d.", i);
}
/* LUT output sel + enable */
for (i = 0; i < 2; ++i) {
temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel);
if (temp < 0) {
report(LL_ERROR,
"Invalid output mux sel '%c' selected for net %d on cell %p.",
lut34->drive_sel[i], i, cell);
errno = EINVAL;
goto fail;
}
BS_SET_BITS(temp, 2, LUT_OUT_BITMAP[i],
"Couldn't set LUT output sel %d for output %d.", temp, i);
}
for (i = 0; i < 4; ++i) {
temp = fpga_cell_lut34_is_driven(lut34->drive_sel[i]);
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
"Couldn't %s output for output %d.",
(!temp ? "enable" : "disabled"), i);
}
/* Routing */
for (i = 0; i < 8; ++i) {
BS_SET_BITS(lut34->route_en, 8, ROUTE_BITMAP,
"Couldn't set routing bitmap to 0x%X for cell %p.",
lut34->route_en, cell);
}
/* LUTD */
if (lut34->LUT4 > -1) {
BS_SET_BITS(lut34->LUT4, 16, LUT4_BITMAP,
"Error setting LUT4 data.");
BS_SET_BIT(BIT_LUT_SPLIT_N, 1, "Couldn't set LUT4 mode.");
}
for (i = 0; i < 2; ++i) {
if (lut34->LUT3[i] > -1) {
BS_SET_BITS(lut34->LUT3[i], 8, LUT3_BITMAP[i],
"Error setting LUT3[%d] data. Did you configure a LUT4 before?",
i);
BS_SET_BIT(BIT_LUT_SPLIT_N, 0, "Couldn't set LUT3-2 mode. Did you configure a LUT4 before?");
}
}
BS_SET_BIT(BIT_LUT_SYNC_N, !lut34->sync, "Couldn't %s synchronous mode.",
(lut34->sync ? "enabling" : "disabling"));
/* Basic check whether each bit has been configured */
for (i = 0; i < cell->type->isp_length; ++i) {
if ((sbuf[i] & 0xFF) != 255) {
report(LL_WARNING,
"Incomplete configuration for cell %p (byte %d: 0x%X).",
cell, i, sbuf[i] & 0xFF);
break;
}
}
report(LL_DEBUG, "Bitstream result for %p:", cell);
for (i = 0; i < 48; ++i) {
report(LL_DEBUG,
" %d: %d%s",
i,
fpga_cell_bitstream_is_set(buf, i),
(fpga_cell_bitstream_is_set(sbuf, i) ? "" : " (Z)"));
}
free(sbuf);
return buf;
fail:
if (buf)
free(buf);
if (sbuf)
free(sbuf);
return NULL;
}

View File

@ -0,0 +1,61 @@
#ifndef FPGA_CELL_LUT34_H
#define FPGA_CELL_LUT34_H
#include "fpga_cell.h"
enum LUT_NET_NAMES {
LUT_NET_DC = '\0', /* Dont' care */
LUT_NET_T0 = '0',
LUT_NET_T1 = '1',
LUT_NET_T2 = '2',
LUT_NET_T3 = '3',
LUT_NET_L0 = 'A',
LUT_NET_L1 = 'B',
LUT_NET_L2 = 'C',
LUT_NET_L3 = 'D',
LUT_NET_F0 = 'W',
LUT_NET_F1 = 'X',
LUT_NET_F2 = 'Y',
LUT_NET_F3 = 'Z'
};
enum LUT_OUT_NAMES {
LUT_OUT_DC = '\0', /* Don't care, treated like Z */
LUT_OUT_Z = 'Z',
LUT_OUT_C = 'C',
LUT_OUT_A = 'A',
LUT_OUT_B = 'B',
LUT_OUT_B_ASYNC = 'b'
};
enum ROUTE_NAMES {
ROUTE_L0 = 0,
ROUTE_L1,
ROUTE_L2,
ROUTE_L3,
ROUTE_T0,
ROUTE_T1,
ROUTE_T2,
ROUTE_T3
};
struct fpga_cell_lut34 {
struct fpga_cell base_cell;
int led_lut_in_enable;
int led_lut_out_enable;
char lut_in_sel[4]; /* Input select */
char drive_sel[4]; /* Which signal to drive onto each fabric line */
int sync; /* Register output on rising edge of clk */
int route_en; /* Bitfield, Enable routing between {left, top} and main fabric */
int LUT4; /* Look-up table for LUT-4 configuration */
int LUT3[2]; /* Look-up tables for LUT-3 configuration */
};
struct fpga_cell *fpga_cell_lut34_new();
struct fpga_cell *fpga_cell_lut34_get_next_isp(struct fpga_cell *cell,
enum fpga_isp_channel *isp_channel);
char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell);
#endif // FPGA_CELL_LUT34_H

View File

@ -0,0 +1,20 @@
#include "fpga_cell_none.h"
#include <stdlib.h>
#include "fpga_global.h"
struct fpga_cell *fpga_cell_none_new()
{
struct fpga_cell_none *fpga_cell_none;
fpga_cell_none = malloc(sizeof(struct fpga_cell_none));
return FPGA_TO_CELL(fpga_cell_none);
}
struct fpga_cell *fpga_cell_none_get_next_isp(struct fpga_cell *fpga_cell,
enum fpga_isp_channel *isp_channel)
{
report(LL_WARNING,
"ISP signal ran into empty cell. Terminating chain.");
return NULL;
}

View File

@ -0,0 +1,14 @@
#ifndef FPGA_CELL_NONE_H
#define FPGA_CELL_NONE_H
#include "fpga_cell.h"
struct fpga_cell_none {
struct fpga_cell base_cell;
};
struct fpga_cell *fpga_cell_none_new();
struct fpga_cell *fpga_cell_none_get_next_isp(struct fpga_cell *fpga_cell,
enum fpga_isp_channel *isp_channel);
#endif // FPGA_CELL_NONE_H

View File

@ -0,0 +1,48 @@
#include "fpga_cell_wire.h"
#include <stdlib.h>
#include "fpga_global.h"
struct fpga_cell *fpga_cell_wire_new()
{
struct fpga_cell_wire *fpga_cell_wire;
fpga_cell_wire = malloc(sizeof(struct fpga_cell_wire));
return FPGA_TO_CELL(fpga_cell_wire);
}
struct fpga_cell *fpga_cell_wire_get_next_isp(struct fpga_cell *cell,
enum fpga_isp_channel *isp_channel)
{
switch (*isp_channel) {
case FPGA_ISP_CHANNEL_NORMAL:
switch (cell->type->identifier) {
case 'P':
return cell->cell_connections[RIGHT];
case ']':
*isp_channel = FPGA_ISP_CHANNEL_BACK;
return cell->cell_connections[LEFT];
default:
goto fail;
}
case FPGA_ISP_CHANNEL_BACK:
switch (cell->type->identifier) {
case 'P':
case '[':
*isp_channel = FPGA_ISP_CHANNEL_LFDN;
return cell->cell_connections[RIGHT];
}
default:
goto fail;
}
fail:
report(LL_ERROR,
"Entered wiring cell %c on invalid ISP channel %d.",
cell->type->identifier, *isp_channel);
*isp_channel = FPGA_ISP_CHANNEL_ERROR;
return NULL;
return NULL;
}

View File

@ -0,0 +1,14 @@
#ifndef FPGA_CELL_WIRE_H
#define FPGA_CELL_WIRE_H
#include "fpga_cell.h"
struct fpga_cell_wire {
struct fpga_cell base_cell;
};
struct fpga_cell *fpga_cell_wire_new();
struct fpga_cell *fpga_cell_wire_get_next_isp(struct fpga_cell *cell,
enum fpga_isp_channel *isp_channel);
#endif // FPGA_CELL_WIRE_H

View File

@ -0,0 +1,60 @@
#include "fpga_fdef_loader.h"
#include <stdio.h>
struct fpga_cell *fpga_fdef_loader_load(char *filename)
{
FILE *fdef;
int c;
int line = 1;
int col = 1;
struct fpga_cell *cell_left = NULL;
struct fpga_cell *cell_top = NULL;
struct fpga_cell *cell = NULL;
report(LL_INFO, "Loading FDEF from %s...", filename);
fdef = fopen(filename, "r");
if (!fdef)
return NULL;
while ((c = fgetc(fdef)) != EOF) {
switch (c) {
case '\n':
col = 0;
line++;
break;
default:
cell = fpga_cell_new((char) c);
if (!cell) {
/* TODO: clean up existing cells */
return NULL;
}
break;
}
if (c == '\n') {
cell_left = NULL;
cell_top = fpga_cell_get_far(cell, LEFT);
report(LL_DEBUG, "");
} else {
if (cell_left)
fpga_cell_connect(cell, cell_left, RIGHT);
if (cell_top)
fpga_cell_connect(cell, cell_top, BOTTOM);
cell_left = cell;
if (cell_top)
cell_top = cell_top->cell_connections[RIGHT];
}
col++;
}
fclose(fdef);
return fpga_cell_get_far(fpga_cell_get_far(cell, LEFT), TOP);
}

View File

@ -0,0 +1,11 @@
#ifndef FPGA_FDEF_LOADER_H
#define FPGA_FDEF_LOADER_H
#include "fpga_global.h"
#include "fpga_cell.h"
#include "fpga_cell_lut34.h"
#include "fpga_cell_none.h"
struct fpga_cell *fpga_fdef_loader_load(char *filename);
#endif // FPGA_FDEF_LOADER_H

View File

@ -0,0 +1,38 @@
#include "fpga_global.h"
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
static int current_log_level = 100;
static const char *ll_string[] = {
"\x1B[31m\x1B[1m[X] ",
"\x1B[31m[E] ",
"\x1B[33m[W] ",
"\x1B[32m[I] ",
"\x1B[34m[D] ",
"[?] "
};
enum log_level report(enum log_level log_level, const char *format, ...)
{
va_list vargs;
if (log_level > LL_COUNT)
log_level = LL_COUNT;
if (log_level <= current_log_level) {
va_start(vargs, format);
fprintf(stderr, "%s", ll_string[log_level]);
vfprintf(stderr, format, vargs);
fprintf(stderr, "\x1B[0m\n");
va_end(vargs);
}
return log_level;
}
void set_log_level(enum log_level log_level)
{
current_log_level = log_level;
}

View File

@ -0,0 +1,20 @@
#ifndef FPGA_GLOBAL_H
#define FPGA_GLOBAL_H
#include <errno.h>
enum log_level {LL_CRITICAL = 0,
LL_ERROR,
LL_WARNING,
LL_INFO,
LL_DEBUG,
LL_COUNT};
enum log_level report(enum log_level log_level, const char *format, ...);
void set_log_level(enum log_level log_level);
/* Error codes */
#define ECONN 1000 /* Tried to connect to already connected port */
#define ETYPE 1001 /* Tried an operation on a cell that does not support it */
#define ERECONF 1100 /* Tried to set a configuration bit to multiple values */
#endif // FPGA_GLOBAL_H

130
sw/kousaten/src/main.c Normal file
View File

@ -0,0 +1,130 @@
#include <stdio.h>
#include "fpga_cell.h"
#include "fpga_fdef_loader.h"
#include "fpga_global.h"
#include "fpga.h"
#include "unistd.h"
#include "string.h"
#include "fpga_cell_lut34.h" /* For testing purposes only */
#define E_FDEF 1
#define E_BITSTREAM 2
static void test_design_cell_ripple(struct fpga_cell_lut34 *cell, int first, int last)
{
cell->lut_in_sel[0] = LUT_NET_F0; // Own state
cell->lut_in_sel[1] = LUT_NET_F2; // Feedback &-net -- just for fun
cell->lut_in_sel[2] = (first ? LUT_NET_T2 : LUT_NET_L1); // &-state of previous stages
cell->lut_in_sel[3] = LUT_NET_L0; // Previous state -- just for fun
cell->sync = 1;
cell->drive_sel[0] = 'A';
cell->drive_sel[1] = 'b';
cell->drive_sel[2] = (last ? 'b' : 'Z');
cell->drive_sel[3] = 'Z';
cell->route_en = (1 << ROUTE_L2);
cell->LUT3[0] = 0b01011010;
cell->LUT3[1] = 0b10100000;
}
// WARNING: Requires a >=4x4 FPGA FDEF!
static void test_design_counter(struct fpga_cell *entry_cell)
{
struct fpga_cell_lut34 *cell;
int i, j;
for (i = 0; i < 4; ++i) {
cell = ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]));
for (j = 4 - i; j < 4; ++j) {
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[BOTTOM];
}
test_design_cell_ripple(cell, 1, 0);
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
test_design_cell_ripple(cell, 0, 0);
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
test_design_cell_ripple(cell, 0, 0);
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
test_design_cell_ripple(cell, 0, 1);
}
}
int development_test_main(int argc, char *argv[])
{
struct fpga_cell *entry_cell;
struct fpga_chain *chain;
int opt;
char *fdef_filename = "fdef/4x4.fdef";
char *kst_filename = "-";
char *bitstream_filename = "-";
int bitstream_ascii = 0;
set_log_level(LL_DEBUG);
while((opt = getopt(argc, argv, "f:i:o:h")) != -1)
{
switch(opt)
{
case 'f':
fdef_filename = optarg;
break;
case 'i':
kst_filename = optarg;
report(LL_WARNING, "Input not yet implemented.");
break;
case 'o':
bitstream_filename = optarg;
break;
case 'h':
bitstream_ascii = 1;
break;
case ':':
case '?':
printf("Usage: %s [-f fdef] [-i input.kst] [-o output.bin] [-h]\n"
"Generate bitstreams for the TTL-FPGA.\n\n"
"When INPUT or OUTPUT is -, read/write standard input.\n\n"
" -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
" -i\tKousaten input file, default stdin\n"
" -o\tOutput file, default stdout\n"
" -h\tGenerate output as ASCII HEX\n",
argv[0]);
return 0;
default:
break;
}
}
entry_cell = fpga_fdef_loader_load(fdef_filename);
if (!entry_cell) {
report(LL_CRITICAL, "Error loading FDEF.");
return E_FDEF;
}
report(LL_INFO, "FDEF loaded.");
chain = fpga_isp_chain_new(entry_cell);
if (!chain) {
report(LL_CRITICAL, "Critical error during bitstream generation.");
return E_BITSTREAM;
}
report(LL_INFO, "Chain loaded.");
test_design_counter(entry_cell);
if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) {
report(LL_ERROR, "Bitstream generation failed.");
return E_BITSTREAM;
}
report(LL_INFO, "Generated bitstream.");
return 0;
}
int main(int argc, char *argv[])
{
return development_test_main(argc, argv);
}