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|
||||
otherwise permitted by the Creative Commons policies published at
|
||||
creativecommons.org/policies, Creative Commons does not authorize the
|
||||
use of the trademark "Creative Commons" or any other trademark or logo
|
||||
of Creative Commons without its prior written consent including,
|
||||
without limitation, in connection with any unauthorized modifications
|
||||
to any of its public licenses or any other arrangements,
|
||||
understandings, or agreements concerning use of licensed material. For
|
||||
the avoidance of doubt, this paragraph does not form part of the
|
||||
public licenses.
|
||||
|
||||
Creative Commons may be contacted at creativecommons.org.
|
||||
|
|
@ -1,2 +1,9 @@
|
|||
# DISCRETE TTL FPGA
|
||||
WIP.
|
||||
Building an FPGA from 74-series logic ICs. For fun and education.
|
||||
|
||||
## License
|
||||
TTL-FPGA, Copyright (C) 2019 Markus Koch <markus@notsyncing.net>
|
||||
|
||||
This work is released under a [Creative Commons Attribution-ShareAlike 4.0 International license](https://creativecommons.org/licenses/by-sa/4.0/).
|
||||
|
||||
You can find a copy of the full license in [LICENSE.txt](./LICENSE.txt).
|
||||
|
|
Binary file not shown.
|
@ -0,0 +1,12 @@
|
|||
# Intro
|
||||
|
||||
* Technology is becoming more complex every day.
|
||||
* Devices get smaller, integration gets higher
|
||||
* As such, it has become harder to actually understand how the devices work.
|
||||
* 80s, you could open your PC and start probing signals on the mainboard to understand which instructions a CPU executed. These days, pretty much everything can be integrated into a single chip and the actual functionality is *built* in software.
|
||||
* One example of such a highly integrated component is the FPGA.
|
||||
* FPGAs essentially allow the designer to create large digital designs inside of an IC.
|
||||
* As these designs are created by writing software-like source code, one might easily forget the fact that what is created is, indeed, a digital circuit.
|
||||
* There is no PCB, no components, but also no visibility of the individual building blocks and connections between them.
|
||||
* To aid students learning about FPGAs better understand the technology, this project aims to provide a platform to look at the inner workings of such a chip by breaking it out of the IC and bringing it onto a PCB where every signal can be traced and measured.
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -7,7 +7,7 @@ encoding utf-8
|
|||
Sheet 3 3
|
||||
Title "DISCRETE TTL FPGA"
|
||||
Date "2019-05-31"
|
||||
Rev "01"
|
||||
Rev "02"
|
||||
Comp "Markus Koch <markus@notsyncing.net>"
|
||||
Comment1 "Logic Block"
|
||||
Comment2 "single 4-input LUT / dual 3-input LUT"
|
||||
|
@ -19,10 +19,10 @@ L 74xx_IEEE:74164 U?
|
|||
U 1 1 5CF42176
|
||||
P 3100 3450
|
||||
AR Path="/5CF41639/5CF42176" Ref="U?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF42176" Ref="U?" Part="1"
|
||||
F 0 "U?" H 3450 3650 50 0000 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF42176" Ref="U13" Part="1"
|
||||
F 0 "U13" H 3450 3650 50 0000 C CNN
|
||||
F 1 "74164" H 3500 3750 50 0000 C CNN
|
||||
F 2 "" H 3100 3450 50 0001 C CNN
|
||||
F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 3100 3450 50 0001 C CNN
|
||||
F 3 "" H 3100 3450 50 0001 C CNN
|
||||
1 3100 3450
|
||||
1 0 0 -1
|
||||
|
@ -32,10 +32,10 @@ L 74xx_IEEE:74164 U?
|
|||
U 1 1 5CF427E5
|
||||
P 3100 5000
|
||||
AR Path="/5CF41639/5CF427E5" Ref="U?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF427E5" Ref="U?" Part="1"
|
||||
F 0 "U?" H 3450 5200 50 0000 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF427E5" Ref="U17" Part="1"
|
||||
F 0 "U17" H 3450 5200 50 0000 C CNN
|
||||
F 1 "74164" H 3500 5300 50 0000 C CNN
|
||||
F 2 "" H 3100 5000 50 0001 C CNN
|
||||
F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 3100 5000 50 0001 C CNN
|
||||
F 3 "" H 3100 5000 50 0001 C CNN
|
||||
1 3100 5000
|
||||
1 0 0 -1
|
||||
|
@ -103,10 +103,10 @@ L 74xx_IEEE:74251 U?
|
|||
U 1 1 5CF5B900
|
||||
P 4800 5200
|
||||
AR Path="/5CF41639/5CF5B900" Ref="U?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF5B900" Ref="U?" Part="1"
|
||||
F 0 "U?" H 5000 5900 50 0000 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF5B900" Ref="U18" Part="1"
|
||||
F 0 "U18" H 5000 5900 50 0000 C CNN
|
||||
F 1 "74251" H 4700 5900 50 0000 C CNN
|
||||
F 2 "" H 4800 5200 50 0001 C CNN
|
||||
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 4800 5200 50 0001 C CNN
|
||||
F 3 "" H 4800 5200 50 0001 C CNN
|
||||
1 4800 5200
|
||||
1 0 0 -1
|
||||
|
@ -144,10 +144,10 @@ L 74xx_IEEE:74251 U?
|
|||
U 1 1 5CF4F8AB
|
||||
P 4800 3650
|
||||
AR Path="/5CF41639/5CF4F8AB" Ref="U?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF4F8AB" Ref="U?" Part="1"
|
||||
F 0 "U?" H 5000 4350 50 0000 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF4F8AB" Ref="U14" Part="1"
|
||||
F 0 "U14" H 5000 4350 50 0000 C CNN
|
||||
F 1 "74251" H 4700 4350 50 0000 C CNN
|
||||
F 2 "" H 4800 3650 50 0001 C CNN
|
||||
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 4800 3650 50 0001 C CNN
|
||||
F 3 "" H 4800 3650 50 0001 C CNN
|
||||
1 4800 3650
|
||||
1 0 0 -1
|
||||
|
@ -192,7 +192,7 @@ Wire Wire Line
|
|||
Text HLabel 2000 5950 0 50 Output ~ 0
|
||||
isp_miso
|
||||
Text HLabel 2000 2700 0 50 Input ~ 0
|
||||
lut_in
|
||||
lut_in[3..0]
|
||||
Text Label 3950 3200 0 50 ~ 0
|
||||
lut_in0
|
||||
Text Label 2050 2700 0 50 ~ 0
|
||||
|
@ -213,8 +213,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D015E6D
|
||||
P 6200 4550
|
||||
AR Path="/5CF41639/5D015E6D" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D015E6D" Ref="#PWR0129" Part="1"
|
||||
F 0 "#PWR0129" H 6200 4300 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D015E6D" Ref="#PWR065" Part="1"
|
||||
F 0 "#PWR065" H 6200 4300 50 0001 C CNN
|
||||
F 1 "GNDD" H 6204 4395 50 0000 C CNN
|
||||
F 2 "" H 6200 4550 50 0001 C CNN
|
||||
F 3 "" H 6200 4550 50 0001 C CNN
|
||||
|
@ -250,10 +250,10 @@ L 74xx_IEEE:74157 U?
|
|||
U 1 1 5D187D09
|
||||
P 9050 4150
|
||||
AR Path="/5CF41639/5D187D09" Ref="U?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D187D09" Ref="U?" Part="1"
|
||||
F 0 "U?" H 9400 4500 50 0000 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D187D09" Ref="U15" Part="1"
|
||||
F 0 "U15" H 9400 4500 50 0000 C CNN
|
||||
F 1 "74157" H 9450 4600 50 0000 C CNN
|
||||
F 2 "" H 9050 4150 50 0001 C CNN
|
||||
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 9050 4150 50 0001 C CNN
|
||||
F 3 "" H 9050 4150 50 0001 C CNN
|
||||
1 9050 4150
|
||||
1 0 0 -1
|
||||
|
@ -263,10 +263,10 @@ L 74xx:74LS174 U?
|
|||
U 1 1 5CF941AD
|
||||
P 6950 4400
|
||||
AR Path="/5CF41639/5CF941AD" Ref="U?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF941AD" Ref="U?" Part="1"
|
||||
F 0 "U?" H 7200 4950 50 0000 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF941AD" Ref="U16" Part="1"
|
||||
F 0 "U16" H 7200 4950 50 0000 C CNN
|
||||
F 1 "74LS174" H 6750 4950 50 0000 C CNN
|
||||
F 2 "" H 6950 4400 50 0001 C CNN
|
||||
F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 6950 4400 50 0001 C CNN
|
||||
F 3 "http://www.ti.com/lit/gpn/sn74LS174" H 6950 4400 50 0001 C CNN
|
||||
1 6950 4400
|
||||
1 0 0 -1
|
||||
|
@ -309,10 +309,10 @@ L Device:R R?
|
|||
U 1 1 5D1A7947
|
||||
P 5550 4350
|
||||
AR Path="/5CF41639/5D1A7947" Ref="R?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D1A7947" Ref="R?" Part="1"
|
||||
F 0 "R?" H 5480 4304 50 0000 R CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D1A7947" Ref="R16" Part="1"
|
||||
F 0 "R16" H 5480 4304 50 0000 R CNN
|
||||
F 1 "10k" H 5480 4395 50 0000 R CNN
|
||||
F 2 "" V 5480 4350 50 0001 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 5480 4350 50 0001 C CNN
|
||||
F 3 "~" H 5550 4350 50 0001 C CNN
|
||||
1 5550 4350
|
||||
1 0 0 1
|
||||
|
@ -322,8 +322,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D1A7DBD
|
||||
P 5550 4600
|
||||
AR Path="/5CF41639/5D1A7DBD" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D1A7DBD" Ref="#PWR0130" Part="1"
|
||||
F 0 "#PWR0130" H 5550 4350 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D1A7DBD" Ref="#PWR066" Part="1"
|
||||
F 0 "#PWR066" H 5550 4350 50 0001 C CNN
|
||||
F 1 "GNDD" H 5554 4445 50 0000 C CNN
|
||||
F 2 "" H 5550 4600 50 0001 C CNN
|
||||
F 3 "" H 5550 4600 50 0001 C CNN
|
||||
|
@ -405,8 +405,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D26A4EB
|
||||
P 6950 5300
|
||||
AR Path="/5CF41639/5D26A4EB" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D26A4EB" Ref="#PWR0132" Part="1"
|
||||
F 0 "#PWR0132" H 6950 5050 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D26A4EB" Ref="#PWR068" Part="1"
|
||||
F 0 "#PWR068" H 6950 5050 50 0001 C CNN
|
||||
F 1 "GNDD" H 6954 5145 50 0000 C CNN
|
||||
F 2 "" H 6950 5300 50 0001 C CNN
|
||||
F 3 "" H 6950 5300 50 0001 C CNN
|
||||
|
@ -420,8 +420,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D276079
|
||||
P 8300 3550
|
||||
AR Path="/5CF41639/5D276079" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D276079" Ref="#PWR0133" Part="1"
|
||||
F 0 "#PWR0133" H 8300 3300 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D276079" Ref="#PWR058" Part="1"
|
||||
F 0 "#PWR058" H 8300 3300 50 0001 C CNN
|
||||
F 1 "GNDD" H 8304 3395 50 0000 C CNN
|
||||
F 2 "" H 8300 3550 50 0001 C CNN
|
||||
F 3 "" H 8300 3550 50 0001 C CNN
|
||||
|
@ -439,8 +439,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D27AEF5
|
||||
P 6950 3600
|
||||
AR Path="/5CF41639/5D27AEF5" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D27AEF5" Ref="#PWR0134" Part="1"
|
||||
F 0 "#PWR0134" H 6950 3450 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D27AEF5" Ref="#PWR060" Part="1"
|
||||
F 0 "#PWR060" H 6950 3450 50 0001 C CNN
|
||||
F 1 "VCC" H 6967 3773 50 0000 C CNN
|
||||
F 2 "" H 6950 3600 50 0001 C CNN
|
||||
F 3 "" H 6950 3600 50 0001 C CNN
|
||||
|
@ -454,8 +454,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D2924B9
|
||||
P 4800 6000
|
||||
AR Path="/5CF41639/5D2924B9" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2924B9" Ref="#PWR0135" Part="1"
|
||||
F 0 "#PWR0135" H 4800 5750 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2924B9" Ref="#PWR069" Part="1"
|
||||
F 0 "#PWR069" H 4800 5750 50 0001 C CNN
|
||||
F 1 "GNDD" H 4804 5845 50 0000 C CNN
|
||||
F 2 "" H 4800 6000 50 0001 C CNN
|
||||
F 3 "" H 4800 6000 50 0001 C CNN
|
||||
|
@ -469,8 +469,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D2970E5
|
||||
P 4450 4400
|
||||
AR Path="/5CF41639/5D2970E5" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2970E5" Ref="#PWR0136" Part="1"
|
||||
F 0 "#PWR0136" H 4450 4150 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2970E5" Ref="#PWR061" Part="1"
|
||||
F 0 "#PWR061" H 4450 4150 50 0001 C CNN
|
||||
F 1 "GNDD" H 4454 4245 50 0000 C CNN
|
||||
F 2 "" H 4450 4400 50 0001 C CNN
|
||||
F 3 "" H 4450 4400 50 0001 C CNN
|
||||
|
@ -486,8 +486,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D29AD03
|
||||
P 5150 4450
|
||||
AR Path="/5CF41639/5D29AD03" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D29AD03" Ref="#PWR0137" Part="1"
|
||||
F 0 "#PWR0137" H 5150 4300 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D29AD03" Ref="#PWR063" Part="1"
|
||||
F 0 "#PWR063" H 5150 4300 50 0001 C CNN
|
||||
F 1 "VCC" H 5167 4623 50 0000 C CNN
|
||||
F 2 "" H 5150 4450 50 0001 C CNN
|
||||
F 3 "" H 5150 4450 50 0001 C CNN
|
||||
|
@ -503,8 +503,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D29EA17
|
||||
P 4800 2900
|
||||
AR Path="/5CF41639/5D29EA17" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D29EA17" Ref="#PWR0138" Part="1"
|
||||
F 0 "#PWR0138" H 4800 2750 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D29EA17" Ref="#PWR054" Part="1"
|
||||
F 0 "#PWR054" H 4800 2750 50 0001 C CNN
|
||||
F 1 "VCC" H 4817 3073 50 0000 C CNN
|
||||
F 2 "" H 4800 2900 50 0001 C CNN
|
||||
F 3 "" H 4800 2900 50 0001 C CNN
|
||||
|
@ -518,8 +518,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D2B29AB
|
||||
P 2900 2850
|
||||
AR Path="/5CF41639/5D2B29AB" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2B29AB" Ref="#PWR0139" Part="1"
|
||||
F 0 "#PWR0139" H 2900 2600 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2B29AB" Ref="#PWR053" Part="1"
|
||||
F 0 "#PWR053" H 2900 2600 50 0001 C CNN
|
||||
F 1 "GNDD" H 2904 2695 50 0000 C CNN
|
||||
F 2 "" H 2900 2850 50 0001 C CNN
|
||||
F 3 "" H 2900 2850 50 0001 C CNN
|
||||
|
@ -537,8 +537,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D2B7E69
|
||||
P 3300 3000
|
||||
AR Path="/5CF41639/5D2B7E69" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2B7E69" Ref="#PWR0140" Part="1"
|
||||
F 0 "#PWR0140" H 3300 2850 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2B7E69" Ref="#PWR055" Part="1"
|
||||
F 0 "#PWR055" H 3300 2850 50 0001 C CNN
|
||||
F 1 "VCC" H 3317 3173 50 0000 C CNN
|
||||
F 2 "" H 3300 3000 50 0001 C CNN
|
||||
F 3 "" H 3300 3000 50 0001 C CNN
|
||||
|
@ -554,8 +554,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D2CD01F
|
||||
P 2900 4450
|
||||
AR Path="/5CF41639/5D2CD01F" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2CD01F" Ref="#PWR0141" Part="1"
|
||||
F 0 "#PWR0141" H 2900 4200 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2CD01F" Ref="#PWR062" Part="1"
|
||||
F 0 "#PWR062" H 2900 4200 50 0001 C CNN
|
||||
F 1 "GNDD" H 2904 4295 50 0000 C CNN
|
||||
F 2 "" H 2900 4450 50 0001 C CNN
|
||||
F 3 "" H 2900 4450 50 0001 C CNN
|
||||
|
@ -571,8 +571,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D2D1794
|
||||
P 3300 4550
|
||||
AR Path="/5CF41639/5D2D1794" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2D1794" Ref="#PWR0142" Part="1"
|
||||
F 0 "#PWR0142" H 3300 4400 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2D1794" Ref="#PWR064" Part="1"
|
||||
F 0 "#PWR064" H 3300 4400 50 0001 C CNN
|
||||
F 1 "VCC" H 3317 4723 50 0000 C CNN
|
||||
F 2 "" H 3300 4550 50 0001 C CNN
|
||||
F 3 "" H 3300 4550 50 0001 C CNN
|
||||
|
@ -602,9 +602,9 @@ L power:GNDD #PWR?
|
|||
U 1 1 5CF3ABB3
|
||||
P 8850 3450
|
||||
AR Path="/5CF41639/5CF3ABB3" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF3ABB3" Ref="#PWR0144" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF3ABB3" Ref="#PWR057" Part="1"
|
||||
AR Path="/5D77FDBE/5CF3ABB3" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0144" H 8850 3200 50 0001 C CNN
|
||||
F 0 "#PWR057" H 8850 3200 50 0001 C CNN
|
||||
F 1 "GNDD" H 8854 3295 50 0000 C CNN
|
||||
F 2 "" H 8850 3450 50 0001 C CNN
|
||||
F 3 "" H 8850 3450 50 0001 C CNN
|
||||
|
@ -620,9 +620,9 @@ L power:VCC #PWR?
|
|||
U 1 1 5CF3ABBB
|
||||
P 9200 3550
|
||||
AR Path="/5CF41639/5CF3ABBB" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF3ABBB" Ref="#PWR0145" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5CF3ABBB" Ref="#PWR059" Part="1"
|
||||
AR Path="/5D77FDBE/5CF3ABBB" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR0145" H 9200 3400 50 0001 C CNN
|
||||
F 0 "#PWR059" H 9200 3400 50 0001 C CNN
|
||||
F 1 "VCC" H 9217 3723 50 0000 C CNN
|
||||
F 2 "" H 9200 3550 50 0001 C CNN
|
||||
F 3 "" H 9200 3550 50 0001 C CNN
|
||||
|
@ -636,10 +636,10 @@ L Device:C C?
|
|||
U 1 1 5D2EACB1
|
||||
P 9500 2050
|
||||
AR Path="/5D77FDBE/5D2EACB1" Ref="C?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACB1" Ref="C?" Part="1"
|
||||
F 0 "C?" H 9500 2150 50 0000 L CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACB1" Ref="C16" Part="1"
|
||||
F 0 "C16" H 9500 2150 50 0000 L CNN
|
||||
F 1 "100n" H 9500 1950 50 0000 L CNN
|
||||
F 2 "" H 9538 1900 50 0001 C CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9538 1900 50 0001 C CNN
|
||||
F 3 "~" H 9500 2050 50 0001 C CNN
|
||||
1 9500 2050
|
||||
1 0 0 -1
|
||||
|
@ -649,10 +649,10 @@ L Device:C C?
|
|||
U 1 1 5D2EACB7
|
||||
P 9700 2050
|
||||
AR Path="/5D77FDBE/5D2EACB7" Ref="C?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACB7" Ref="C?" Part="1"
|
||||
F 0 "C?" H 9700 2150 50 0000 L CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACB7" Ref="C17" Part="1"
|
||||
F 0 "C17" H 9700 2150 50 0000 L CNN
|
||||
F 1 "100n" H 9700 1950 50 0000 L CNN
|
||||
F 2 "" H 9738 1900 50 0001 C CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9738 1900 50 0001 C CNN
|
||||
F 3 "~" H 9700 2050 50 0001 C CNN
|
||||
1 9700 2050
|
||||
1 0 0 -1
|
||||
|
@ -662,10 +662,10 @@ L Device:C C?
|
|||
U 1 1 5D2EACBD
|
||||
P 9900 2050
|
||||
AR Path="/5D77FDBE/5D2EACBD" Ref="C?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACBD" Ref="C?" Part="1"
|
||||
F 0 "C?" H 9900 2150 50 0000 L CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACBD" Ref="C18" Part="1"
|
||||
F 0 "C18" H 9900 2150 50 0000 L CNN
|
||||
F 1 "100n" H 9900 1950 50 0000 L CNN
|
||||
F 2 "" H 9938 1900 50 0001 C CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9938 1900 50 0001 C CNN
|
||||
F 3 "~" H 9900 2050 50 0001 C CNN
|
||||
1 9900 2050
|
||||
1 0 0 -1
|
||||
|
@ -675,10 +675,10 @@ L Device:C C?
|
|||
U 1 1 5D2EACC3
|
||||
P 10100 2050
|
||||
AR Path="/5D77FDBE/5D2EACC3" Ref="C?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACC3" Ref="C?" Part="1"
|
||||
F 0 "C?" H 10100 2150 50 0000 L CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACC3" Ref="C19" Part="1"
|
||||
F 0 "C19" H 10100 2150 50 0000 L CNN
|
||||
F 1 "100n" H 10100 1950 50 0000 L CNN
|
||||
F 2 "" H 10138 1900 50 0001 C CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 10138 1900 50 0001 C CNN
|
||||
F 3 "~" H 10100 2050 50 0001 C CNN
|
||||
1 10100 2050
|
||||
1 0 0 -1
|
||||
|
@ -716,8 +716,8 @@ L power:GNDD #PWR?
|
|||
U 1 1 5D2EACE7
|
||||
P 9700 2400
|
||||
AR Path="/5D77FDBE/5D2EACE7" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACE7" Ref="#PWR0147" Part="1"
|
||||
F 0 "#PWR0147" H 9700 2150 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACE7" Ref="#PWR052" Part="1"
|
||||
F 0 "#PWR052" H 9700 2150 50 0001 C CNN
|
||||
F 1 "GNDD" H 9704 2245 50 0000 C CNN
|
||||
F 2 "" H 9700 2400 50 0001 C CNN
|
||||
F 3 "" H 9700 2400 50 0001 C CNN
|
||||
|
@ -729,10 +729,10 @@ L Device:C C?
|
|||
U 1 1 5D2FCD73
|
||||
P 10300 2050
|
||||
AR Path="/5D77FDBE/5D2FCD73" Ref="C?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2FCD73" Ref="C?" Part="1"
|
||||
F 0 "C?" H 10300 2150 50 0000 L CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2FCD73" Ref="C20" Part="1"
|
||||
F 0 "C20" H 10300 2150 50 0000 L CNN
|
||||
F 1 "100n" H 10300 1950 50 0000 L CNN
|
||||
F 2 "" H 10338 1900 50 0001 C CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 10338 1900 50 0001 C CNN
|
||||
F 3 "~" H 10300 2050 50 0001 C CNN
|
||||
1 10300 2050
|
||||
1 0 0 -1
|
||||
|
@ -742,10 +742,10 @@ L Device:C C?
|
|||
U 1 1 5D2FCFE7
|
||||
P 9300 2050
|
||||
AR Path="/5D77FDBE/5D2FCFE7" Ref="C?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2FCFE7" Ref="C?" Part="1"
|
||||
F 0 "C?" H 9300 2150 50 0000 L CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2FCFE7" Ref="C15" Part="1"
|
||||
F 0 "C15" H 9300 2150 50 0000 L CNN
|
||||
F 1 "100n" H 9300 1950 50 0000 L CNN
|
||||
F 2 "" H 9338 1900 50 0001 C CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9338 1900 50 0001 C CNN
|
||||
F 3 "~" H 9300 2050 50 0001 C CNN
|
||||
1 9300 2050
|
||||
1 0 0 -1
|
||||
|
@ -785,10 +785,10 @@ L Device:C C?
|
|||
U 1 1 5D182B36
|
||||
P 9100 2050
|
||||
AR Path="/5D77FDBE/5D182B36" Ref="C?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D182B36" Ref="C?" Part="1"
|
||||
F 0 "C?" H 9100 2150 50 0000 L CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D182B36" Ref="C14" Part="1"
|
||||
F 0 "C14" H 9100 2150 50 0000 L CNN
|
||||
F 1 "100n" H 9100 1950 50 0000 L CNN
|
||||
F 2 "" H 9138 1900 50 0001 C CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 9138 1900 50 0001 C CNN
|
||||
F 3 "~" H 9100 2050 50 0001 C CNN
|
||||
1 9100 2050
|
||||
1 0 0 -1
|
||||
|
@ -808,8 +808,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D2EACE1
|
||||
P 9700 1700
|
||||
AR Path="/5D77FDBE/5D2EACE1" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACE1" Ref="#PWR0146" Part="1"
|
||||
F 0 "#PWR0146" H 9700 1550 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D2EACE1" Ref="#PWR051" Part="1"
|
||||
F 0 "#PWR051" H 9700 1550 50 0001 C CNN
|
||||
F 1 "VCC" H 9717 1873 50 0000 C CNN
|
||||
F 2 "" H 9700 1700 50 0001 C CNN
|
||||
F 3 "" H 9700 1700 50 0001 C CNN
|
||||
|
@ -837,12 +837,12 @@ lut_in3_n
|
|||
Text Label 3950 2150 2 50 ~ 0
|
||||
lut_b_en_n
|
||||
$Comp
|
||||
L Device:R R?
|
||||
L Device:R R15
|
||||
U 1 1 5D4D5C26
|
||||
P 4150 2150
|
||||
F 0 "R?" H 4220 2196 50 0000 L CNN
|
||||
F 0 "R15" H 4220 2196 50 0000 L CNN
|
||||
F 1 "10k" H 4220 2105 50 0000 L CNN
|
||||
F 2 "" V 4080 2150 50 0001 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 4080 2150 50 0001 C CNN
|
||||
F 3 "~" H 4150 2150 50 0001 C CNN
|
||||
1 4150 2150
|
||||
1 0 0 -1
|
||||
|
@ -859,12 +859,12 @@ Wire Wire Line
|
|||
Wire Wire Line
|
||||
4150 2400 3950 2400
|
||||
$Comp
|
||||
L Device:D_Schottky D?
|
||||
L Device:D_Schottky D11
|
||||
U 1 1 5D50C782
|
||||
P 3800 2400
|
||||
F 0 "D?" H 3800 2500 50 0000 C CNN
|
||||
F 0 "D11" H 3800 2500 50 0000 C CNN
|
||||
F 1 "D_Schottky" H 3800 2300 50 0000 C CNN
|
||||
F 2 "" H 3800 2400 50 0001 C CNN
|
||||
F 2 "Diode_SMD:D_0603_1608Metric" H 3800 2400 50 0001 C CNN
|
||||
F 3 "~" H 3800 2400 50 0001 C CNN
|
||||
1 3800 2400
|
||||
1 0 0 -1
|
||||
|
@ -874,23 +874,23 @@ Wire Wire Line
|
|||
Text Label 4550 2400 2 50 ~ 0
|
||||
lut_a_en_n
|
||||
$Comp
|
||||
L Device:R R?
|
||||
L Device:R R14
|
||||
U 1 1 5D544A69
|
||||
P 3500 1900
|
||||
F 0 "R?" H 3570 1946 50 0000 L CNN
|
||||
F 0 "R14" H 3570 1946 50 0000 L CNN
|
||||
F 1 "10k" H 3570 1855 50 0000 L CNN
|
||||
F 2 "" V 3430 1900 50 0001 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 3430 1900 50 0001 C CNN
|
||||
F 3 "~" H 3500 1900 50 0001 C CNN
|
||||
1 3500 1900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:D_Schottky D?
|
||||
L Device:D_Schottky D10
|
||||
U 1 1 5D544D70
|
||||
P 3150 2150
|
||||
F 0 "D?" H 3150 2250 50 0000 C CNN
|
||||
F 0 "D10" H 3150 2250 50 0000 C CNN
|
||||
F 1 "D_Schottky" H 3150 2050 50 0000 C CNN
|
||||
F 2 "" H 3150 2150 50 0001 C CNN
|
||||
F 2 "Diode_SMD:D_0603_1608Metric" H 3150 2150 50 0001 C CNN
|
||||
F 3 "~" H 3150 2150 50 0001 C CNN
|
||||
1 3150 2150
|
||||
1 0 0 -1
|
||||
|
@ -916,8 +916,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D6F060A
|
||||
P 2450 3100
|
||||
AR Path="/5CF41639/5D6F060A" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D6F060A" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR?" H 2450 2950 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D6F060A" Ref="#PWR056" Part="1"
|
||||
F 0 "#PWR056" H 2450 2950 50 0001 C CNN
|
||||
F 1 "VCC" H 2467 3273 50 0000 C CNN
|
||||
F 2 "" H 2450 3100 50 0001 C CNN
|
||||
F 3 "" H 2450 3100 50 0001 C CNN
|
||||
|
@ -933,8 +933,8 @@ L power:VCC #PWR?
|
|||
U 1 1 5D6F756A
|
||||
P 2550 4650
|
||||
AR Path="/5CF41639/5D6F756A" Ref="#PWR?" Part="1"
|
||||
AR Path="/5D77FDBE/5D7AF013/5D6F756A" Ref="#PWR?" Part="1"
|
||||
F 0 "#PWR?" H 2550 4500 50 0001 C CNN
|
||||
AR Path="/5D77FDBE/5D7AF013/5D6F756A" Ref="#PWR067" Part="1"
|
||||
F 0 "#PWR067" H 2550 4500 50 0001 C CNN
|
||||
F 1 "VCC" H 2567 4823 50 0000 C CNN
|
||||
F 2 "" H 2550 4650 50 0001 C CNN
|
||||
F 3 "" H 2550 4650 50 0001 C CNN
|
||||
|
@ -944,23 +944,23 @@ $EndComp
|
|||
Wire Wire Line
|
||||
2550 4650 2550 4750
|
||||
$Comp
|
||||
L Device:D_Schottky D?
|
||||
L Device:D_Schottky D12
|
||||
U 1 1 5D7F6986
|
||||
P 5800 3650
|
||||
F 0 "D?" H 5800 3750 50 0000 C CNN
|
||||
F 0 "D12" H 5800 3750 50 0000 C CNN
|
||||
F 1 "D_Schottky" H 5800 3550 50 0000 C CNN
|
||||
F 2 "" H 5800 3650 50 0001 C CNN
|
||||
F 2 "Diode_SMD:D_0603_1608Metric" H 5800 3650 50 0001 C CNN
|
||||
F 3 "~" H 5800 3650 50 0001 C CNN
|
||||
1 5800 3650
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:D_Schottky D?
|
||||
L Device:D_Schottky D13
|
||||
U 1 1 5D7F6FF8
|
||||
P 5800 4500
|
||||
F 0 "D?" H 5800 4600 50 0000 C CNN
|
||||
F 0 "D13" H 5800 4600 50 0000 C CNN
|
||||
F 1 "D_Schottky" H 5800 4400 50 0000 C CNN
|
||||
F 2 "" H 5800 4500 50 0001 C CNN
|
||||
F 2 "Diode_SMD:D_0603_1608Metric" H 5800 4500 50 0001 C CNN
|
||||
F 3 "~" H 5800 4500 50 0001 C CNN
|
||||
1 5800 4500
|
||||
0 1 1 0
|
|
@ -325,6 +325,26 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
|
|||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_CP
|
||||
#
|
||||
DEF Device_CP C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_CP" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
CP_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -90 20 90 40 0 1 0 N
|
||||
S 90 -20 -90 -40 0 1 0 F
|
||||
P 2 0 1 0 -70 90 -30 90 N
|
||||
P 2 0 1 0 -50 110 -50 70 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_D_Schottky
|
||||
#
|
||||
DEF Device_D_Schottky D 0 40 N N 1 F N
|
|
@ -1,4 +1,4 @@
|
|||
update=Thu 30 May 2019 02:28:07 PM CEST
|
||||
update=Sat 01 Jun 2019 09:25:42 PM CEST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
|
@ -22,15 +22,15 @@ AllowMicroVias=0
|
|||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinTrackWidth=0.1524
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
TrackWidth1=0.1524
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
|
@ -57,7 +57,7 @@ OthersTextUpright=1
|
|||
SolderMaskClearance=0.051
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
|
@ -223,14 +223,14 @@ Enabled=1
|
|||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=1
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
Clearance=0.1524
|
||||
TrackWidth=0.1524
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
|
@ -7,7 +7,7 @@ encoding utf-8
|
|||
Sheet 1 3
|
||||
Title "DISCRETE TTL FPGA"
|
||||
Date "2019-05-31"
|
||||
Rev "01"
|
||||
Rev "02"
|
||||
Comp "Markus Koch <markus@notsyncing.net>"
|
||||
Comment1 "PCB"
|
||||
Comment2 ""
|
||||
|
@ -19,10 +19,10 @@ Wire Wire Line
|
|||
Wire Wire Line
|
||||
7900 3350 7900 3250
|
||||
$Comp
|
||||
L power:VCC #PWR?
|
||||
L power:VCC #PWR04
|
||||
U 1 1 5FF9C392
|
||||
P 7900 3250
|
||||
F 0 "#PWR?" H 7900 3100 50 0001 C CNN
|
||||
F 0 "#PWR04" H 7900 3100 50 0001 C CNN
|
||||
F 1 "VCC" H 7917 3423 50 0000 C CNN
|
||||
F 2 "" H 7900 3250 50 0001 C CNN
|
||||
F 3 "" H 7900 3250 50 0001 C CNN
|
||||
|
@ -30,10 +30,10 @@ F 3 "" H 7900 3250 50 0001 C CNN
|
|||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDD #PWR?
|
||||
L power:GNDD #PWR06
|
||||
U 1 1 5FF9C39C
|
||||
P 7800 3450
|
||||
F 0 "#PWR?" H 7800 3200 50 0001 C CNN
|
||||
F 0 "#PWR06" H 7800 3200 50 0001 C CNN
|
||||
F 1 "GNDD" V 7804 3340 50 0000 R CNN
|
||||
F 2 "" H 7800 3450 50 0001 C CNN
|
||||
F 3 "" H 7800 3450 50 0001 C CNN
|
||||
|
@ -164,10 +164,10 @@ Wire Wire Line
|
|||
Wire Wire Line
|
||||
3550 3450 3350 3450
|
||||
$Comp
|
||||
L power:GNDD #PWR?
|
||||
L power:GNDD #PWR05
|
||||
U 1 1 5FE8BD0F
|
||||
P 3550 3450
|
||||
F 0 "#PWR?" H 3550 3200 50 0001 C CNN
|
||||
F 0 "#PWR05" H 3550 3200 50 0001 C CNN
|
||||
F 1 "GNDD" V 3554 3340 50 0000 R CNN
|
||||
F 2 "" H 3550 3450 50 0001 C CNN
|
||||
F 3 "" H 3550 3450 50 0001 C CNN
|
||||
|
@ -175,10 +175,10 @@ F 3 "" H 3550 3450 50 0001 C CNN
|
|||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:VCC #PWR?
|
||||
L power:VCC #PWR03
|
||||
U 1 1 5FE8B843
|
||||
P 3450 3250
|
||||
F 0 "#PWR?" H 3450 3100 50 0001 C CNN
|
||||
F 0 "#PWR03" H 3450 3100 50 0001 C CNN
|
||||
F 1 "VCC" H 3467 3423 50 0000 C CNN
|
||||
F 2 "" H 3450 3250 50 0001 C CNN
|
||||
F 3 "" H 3450 3250 50 0001 C CNN
|
||||
|
@ -189,17 +189,6 @@ Wire Wire Line
|
|||
3450 3350 3450 3250
|
||||
Wire Wire Line
|
||||
3350 3350 3450 3350
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Female J?
|
||||
U 1 1 5FE88CA2
|
||||
P 3150 3850
|
||||
F 0 "J?" H 3100 4450 50 0000 C CNN
|
||||
F 1 "Left" H 3050 3200 50 0000 C CNN
|
||||
F 2 "" H 3150 3850 50 0001 C CNN
|
||||
F 3 "~" H 3150 3850 50 0001 C CNN
|
||||
1 3150 3850
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6800 3400 7100 3400
|
||||
Text Label 3950 4550 0 50 ~ 0
|
||||
|
@ -217,10 +206,10 @@ VCC\nGND\nCLK\nRST\nSCK\nmiso\nmosi\n\nI0\nI1\nI2\nI3
|
|||
Wire Wire Line
|
||||
5250 5600 5250 5550
|
||||
$Comp
|
||||
L power:VCC #PWR?
|
||||
L power:VCC #PWR012
|
||||
U 1 1 60046AFF
|
||||
P 5250 5550
|
||||
F 0 "#PWR?" H 5250 5400 50 0001 C CNN
|
||||
F 0 "#PWR012" H 5250 5400 50 0001 C CNN
|
||||
F 1 "VCC" H 5150 5650 50 0000 C CNN
|
||||
F 2 "" H 5250 5550 50 0001 C CNN
|
||||
F 3 "" H 5250 5550 50 0001 C CNN
|
||||
|
@ -228,10 +217,10 @@ F 3 "" H 5250 5550 50 0001 C CNN
|
|||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDD #PWR?
|
||||
L power:GNDD #PWR09
|
||||
U 1 1 60046AF5
|
||||
P 5200 5200
|
||||
F 0 "#PWR?" H 5200 4950 50 0001 C CNN
|
||||
F 0 "#PWR09" H 5200 4950 50 0001 C CNN
|
||||
F 1 "GNDD" H 5204 5045 50 0000 C CNN
|
||||
F 2 "" H 5200 5200 50 0001 C CNN
|
||||
F 3 "" H 5200 5200 50 0001 C CNN
|
||||
|
@ -307,23 +296,23 @@ Wire Wire Line
|
|||
Text Notes 6400 5850 3 63 ~ 0
|
||||
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI0\nI1\nI2\nI3
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Female J?
|
||||
L Connector:Conn_01x12_Female J4
|
||||
U 1 1 60090C3D
|
||||
P 5750 1850
|
||||
F 0 "J?" H 5700 2450 50 0000 C CNN
|
||||
F 1 "Top" V 5650 1150 50 0000 C CNN
|
||||
F 2 "" H 5750 1850 50 0001 C CNN
|
||||
F 3 "~" H 5750 1850 50 0001 C CNN
|
||||
1 5750 1850
|
||||
0 -1 -1 0
|
||||
P 5750 5800
|
||||
F 0 "J4" H 5700 6400 50 0000 C CNN
|
||||
F 1 "Bottom" V 5650 5050 50 0000 C CNN
|
||||
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 5750 5800 50 0001 C CNN
|
||||
F 3 "~" H 5750 5800 50 0001 C CNN
|
||||
1 5750 5800
|
||||
0 -1 1 0
|
||||
$EndComp
|
||||
Text Notes 6400 1800 1 63 ~ 0
|
||||
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI0\nI1\nI2\nI3
|
||||
$Comp
|
||||
L power:VCC #PWR?
|
||||
L power:VCC #PWR01
|
||||
U 1 1 600A7963
|
||||
P 5150 2150
|
||||
F 0 "#PWR?" H 5150 2000 50 0001 C CNN
|
||||
F 0 "#PWR01" H 5150 2000 50 0001 C CNN
|
||||
F 1 "VCC" H 5250 2200 50 0000 C CNN
|
||||
F 2 "" H 5150 2150 50 0001 C CNN
|
||||
F 3 "" H 5150 2150 50 0001 C CNN
|
||||
|
@ -450,10 +439,10 @@ Wire Wire Line
|
|||
Wire Wire Line
|
||||
5350 2250 5350 2050
|
||||
$Comp
|
||||
L power:GNDD #PWR?
|
||||
L power:GNDD #PWR02
|
||||
U 1 1 600A7959
|
||||
P 5350 2250
|
||||
F 0 "#PWR?" H 5350 2000 50 0001 C CNN
|
||||
F 0 "#PWR02" H 5350 2000 50 0001 C CNN
|
||||
F 1 "GNDD" H 5354 2095 50 0000 C CNN
|
||||
F 2 "" H 5350 2250 50 0001 C CNN
|
||||
F 3 "" H 5350 2250 50 0001 C CNN
|
||||
|
@ -476,27 +465,135 @@ Wire Notes Line
|
|||
Wire Notes Line
|
||||
3150 5800 3150 1850
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Male J?
|
||||
L Connector:Conn_01x12_Male J1
|
||||
U 1 1 5CF30EFB
|
||||
P 5750 1850
|
||||
F 0 "J1" H 5850 2450 50 0000 R CNN
|
||||
F 1 "Top" V 5850 1200 50 0000 R CNN
|
||||
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 5750 1850 50 0001 C CNN
|
||||
F 3 "~" H 5750 1850 50 0001 C CNN
|
||||
1 5750 1850
|
||||
0 -1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Male J3
|
||||
U 1 1 5CF23FEF
|
||||
P 8200 3850
|
||||
F 0 "J?" H 8300 4450 50 0000 R CNN
|
||||
F 0 "J3" H 8300 4450 50 0000 R CNN
|
||||
F 1 "Right" H 8400 3200 50 0000 R CNN
|
||||
F 2 "" H 8200 3850 50 0001 C CNN
|
||||
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 8200 3850 50 0001 C CNN
|
||||
F 3 "~" H 8200 3850 50 0001 C CNN
|
||||
1 8200 3850
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Male J?
|
||||
U 1 1 5CF30EFB
|
||||
P 5750 5800
|
||||
F 0 "J?" H 5850 6400 50 0000 R CNN
|
||||
F 1 "Bottom" V 5850 5150 50 0000 R CNN
|
||||
F 2 "" H 5750 5800 50 0001 C CNN
|
||||
F 3 "~" H 5750 5800 50 0001 C CNN
|
||||
1 5750 5800
|
||||
L Connector:Conn_01x12_Female J2
|
||||
U 1 1 5FE88CA2
|
||||
P 3150 3850
|
||||
F 0 "J2" H 3100 4450 50 0000 C CNN
|
||||
F 1 "Left" H 3050 3200 50 0000 C CNN
|
||||
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 3150 3850 50 0001 C CNN
|
||||
F 3 "~" H 3150 3850 50 0001 C CNN
|
||||
1 3150 3850
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:CP C1
|
||||
U 1 1 5CF70F0E
|
||||
P 3550 5150
|
||||
F 0 "C1" H 3668 5196 50 0000 L CNN
|
||||
F 1 "10u" H 3668 5105 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_1206_3216Metric" H 3588 5000 50 0001 C CNN
|
||||
F 3 "~" H 3550 5150 50 0001 C CNN
|
||||
1 3550 5150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:VCC #PWR07
|
||||
U 1 1 5CF715DB
|
||||
P 3550 4900
|
||||
F 0 "#PWR07" H 3550 4750 50 0001 C CNN
|
||||
F 1 "VCC" H 3567 5073 50 0000 C CNN
|
||||
F 2 "" H 3550 4900 50 0001 C CNN
|
||||
F 3 "" H 3550 4900 50 0001 C CNN
|
||||
1 3550 4900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3550 5000 3550 4900
|
||||
$Comp
|
||||
L Device:LED D?
|
||||
U 1 1 5CFB92E6
|
||||
P 4150 5200
|
||||
AR Path="/5D77FDBE/5D7AF013/5CFB92E6" Ref="D?" Part="1"
|
||||
AR Path="/5D77FDBE/5CFB92E6" Ref="D?" Part="1"
|
||||
AR Path="/5CFB92E6" Ref="D1" Part="1"
|
||||
F 0 "D1" V 4200 5100 50 0000 R CNN
|
||||
F 1 "PWR" V 4100 5100 50 0000 R CNN
|
||||
F 2 "LED_SMD:LED_0603_1608Metric" H 4150 5200 50 0001 C CNN
|
||||
F 3 "~" H 4150 5200 50 0001 C CNN
|
||||
1 4150 5200
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R R?
|
||||
U 1 1 5CFB92EC
|
||||
P 3950 5000
|
||||
AR Path="/5D77FDBE/5D7AF013/5CFB92EC" Ref="R?" Part="1"
|
||||
AR Path="/5D77FDBE/5CFB92EC" Ref="R?" Part="1"
|
||||
AR Path="/5CFB92EC" Ref="R1" Part="1"
|
||||
F 0 "R1" H 4020 5046 50 0000 L CNN
|
||||
F 1 "470" H 4020 4955 50 0000 L CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 3880 5000 50 0001 C CNN
|
||||
F 3 "~" H 3950 5000 50 0001 C CNN
|
||||
1 3950 5000
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:VCC #PWR08
|
||||
U 1 1 5CFBED78
|
||||
P 3750 4900
|
||||
F 0 "#PWR08" H 3750 4750 50 0001 C CNN
|
||||
F 1 "VCC" H 3767 5073 50 0000 C CNN
|
||||
F 2 "" H 3750 4900 50 0001 C CNN
|
||||
F 3 "" H 3750 4900 50 0001 C CNN
|
||||
1 3750 4900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3800 5000 3750 5000
|
||||
Wire Wire Line
|
||||
3750 5000 3750 4900
|
||||
Wire Wire Line
|
||||
4100 5000 4150 5000
|
||||
Wire Wire Line
|
||||
4150 5000 4150 5050
|
||||
Wire Wire Line
|
||||
3550 5400 3550 5300
|
||||
$Comp
|
||||
L power:GNDD #PWR010
|
||||
U 1 1 5CF71B50
|
||||
P 3550 5400
|
||||
F 0 "#PWR010" H 3550 5150 50 0001 C CNN
|
||||
F 1 "GNDD" V 3554 5290 50 0000 R CNN
|
||||
F 2 "" H 3550 5400 50 0001 C CNN
|
||||
F 3 "" H 3550 5400 50 0001 C CNN
|
||||
1 3550 5400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4150 5350 4150 5400
|
||||
$Comp
|
||||
L power:GNDD #PWR011
|
||||
U 1 1 5CFBCC03
|
||||
P 4150 5400
|
||||
F 0 "#PWR011" H 4150 5150 50 0001 C CNN
|
||||
F 1 "GNDD" V 4154 5290 50 0000 R CNN
|
||||
F 2 "" H 4150 5400 50 0001 C CNN
|
||||
F 3 "" H 4150 5400 50 0001 C CNN
|
||||
1 4150 5400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Bus Line
|
||||
7450 4250 7450 4550
|
||||
Wire Bus Line
|
|
@ -0,0 +1,3 @@
|
|||
(fp_lib_table
|
||||
(lib (name lib_mokmod)(type KiCad)(uri ${KIPRJMOD})(options "")(descr ""))
|
||||
)
|
|
@ -0,0 +1,358 @@
|
|||
(module LOGO (layer F.Cu)
|
||||
(at 0 0)
|
||||
(fp_text reference "G***" (at 0 0) (layer F.SilkS) hide
|
||||
(effects (font (thickness 0.3)))
|
||||
)
|
||||
(fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
|
||||
(effects (font (thickness 0.3)))
|
||||
)
|
||||
(fp_poly (pts (xy 3.335488 0.217118) (xy 3.390515 0.219364) (xy 3.392954 0.558031) (xy 3.393295 0.648329) (xy 3.393115 0.747088) (xy 3.392455 0.852171) (xy 3.391353 0.961441) (xy 3.389851 1.072763)
|
||||
(xy 3.387987 1.183999) (xy 3.385802 1.293014) (xy 3.383335 1.397671) (xy 3.380626 1.495833) (xy 3.377716 1.585366) (xy 3.374643 1.664131) (xy 3.371449 1.729993) (xy 3.370910 1.739516)
|
||||
(xy 3.365600 1.832800) (xy 3.361066 1.916615) (xy 3.357193 1.993969) (xy 3.353864 2.067865) (xy 3.350963 2.141308) (xy 3.348373 2.217305) (xy 3.345978 2.298861) (xy 3.343662 2.388980)
|
||||
(xy 3.341308 2.490669) (xy 3.340645 2.520758) (xy 3.337407 2.667333) (xy 3.334396 2.799432) (xy 3.331568 2.917968) (xy 3.328883 3.023856) (xy 3.326295 3.118012) (xy 3.323764 3.201348)
|
||||
(xy 3.321245 3.274781) (xy 3.318696 3.339224) (xy 3.316074 3.395593) (xy 3.313336 3.444801) (xy 3.310440 3.487764) (xy 3.307342 3.525396) (xy 3.304000 3.558611) (xy 3.300371 3.588325)
|
||||
(xy 3.296412 3.615452) (xy 3.292080 3.640906) (xy 3.287333 3.665602) (xy 3.286927 3.667607) (xy 3.269294 3.739103) (xy 3.247683 3.797251) (xy 3.221002 3.843823) (xy 3.188165 3.880592)
|
||||
(xy 3.148081 3.909328) (xy 3.133589 3.917095) (xy 3.103233 3.931578) (xy 3.076144 3.942386) (xy 3.048256 3.950597) (xy 3.015506 3.957290) (xy 2.973827 3.963543) (xy 2.944091 3.967378)
|
||||
(xy 2.864868 3.976185) (xy 2.770725 3.984739) (xy 2.662136 3.993022) (xy 2.539573 4.001017) (xy 2.403509 4.008706) (xy 2.254417 4.016072) (xy 2.092769 4.023098) (xy 1.919037 4.029766)
|
||||
(xy 1.733696 4.036058) (xy 1.537217 4.041957) (xy 1.330074 4.047446) (xy 1.112739 4.052507) (xy 0.885684 4.057123) (xy 0.649383 4.061277) (xy 0.404308 4.064950) (xy 0.242454 4.067049)
|
||||
(xy -0.050031 4.070616) (xy -0.079057 4.033178) (xy -0.102957 3.997871) (xy -0.119384 3.961519) (xy -0.129819 3.919630) (xy -0.135744 3.867710) (xy -0.136281 3.859662) (xy -0.136377 3.853671)
|
||||
(xy -0.023091 3.853671) (xy -0.023091 3.940849) (xy 0.459894 3.940755) (xy 0.556114 3.940602) (xy 0.656695 3.940197) (xy 0.759020 3.939566) (xy 0.860475 3.938733) (xy 0.958444 3.937726)
|
||||
(xy 1.050312 3.936569) (xy 1.133464 3.935288) (xy 1.205285 3.933909) (xy 1.239212 3.933112) (xy 1.408900 3.928490) (xy 1.574765 3.923380) (xy 1.735815 3.917835) (xy 1.891054 3.911902)
|
||||
(xy 2.039491 3.905634) (xy 2.180130 3.899081) (xy 2.311980 3.892292) (xy 2.434046 3.885317) (xy 2.545335 3.878208) (xy 2.644853 3.871014) (xy 2.731608 3.863785) (xy 2.804605 3.856573)
|
||||
(xy 2.844030 3.851939) (xy 2.921040 3.840802) (xy 2.984293 3.828349) (xy 3.035421 3.813761) (xy 3.076053 3.796223) (xy 3.107820 3.774919) (xy 3.132351 3.749031) (xy 3.151275 3.717744)
|
||||
(xy 3.161858 3.692742) (xy 3.174572 3.650444) (xy 3.186498 3.595304) (xy 3.197187 3.529868) (xy 3.206191 3.456685) (xy 3.209550 3.422158) (xy 3.212692 3.379905) (xy 3.215815 3.324442)
|
||||
(xy 3.218858 3.257952) (xy 3.221757 3.182619) (xy 3.224447 3.100626) (xy 3.226865 3.014158) (xy 3.228948 2.925398) (xy 3.230632 2.836530) (xy 3.231854 2.749736) (xy 3.232548 2.667201)
|
||||
(xy 3.232678 2.628516) (xy 3.233403 2.525290) (xy 3.235212 2.418893) (xy 3.237996 2.312509) (xy 3.241645 2.209325) (xy 3.246048 2.112525) (xy 3.251097 2.025296) (xy 3.255674 1.962728)
|
||||
(xy 3.258430 1.925334) (xy 3.261549 1.876577) (xy 3.264798 1.820473) (xy 3.267949 1.761042) (xy 3.270771 1.702301) (xy 3.271342 1.689485) (xy 3.272581 1.656172) (xy 3.273915 1.611293)
|
||||
(xy 3.275323 1.556188) (xy 3.276786 1.492193) (xy 3.278285 1.420648) (xy 3.279800 1.342889) (xy 3.281310 1.260256) (xy 3.282798 1.174086) (xy 3.284243 1.085716) (xy 3.285626 0.996486)
|
||||
(xy 3.286927 0.907733) (xy 3.288127 0.820795) (xy 3.289205 0.737010) (xy 3.290144 0.657716) (xy 3.290923 0.584251) (xy 3.291522 0.517954) (xy 3.291922 0.460162) (xy 3.292104 0.412213)
|
||||
(xy 3.292048 0.375445) (xy 3.291734 0.351197) (xy 3.291143 0.340806) (xy 3.291032 0.340528) (xy 3.282782 0.341040) (xy 3.261849 0.344516) (xy 3.230547 0.350458) (xy 3.191193 0.358366)
|
||||
(xy 3.146102 0.367741) (xy 3.097590 0.378085) (xy 3.047973 0.388898) (xy 2.999566 0.399681) (xy 2.954684 0.409936) (xy 2.915644 0.419164) (xy 2.884761 0.426865) (xy 2.865165 0.432289)
|
||||
(xy 2.832375 0.444851) (xy 2.811197 0.458432) (xy 2.806422 0.464062) (xy 2.800926 0.480942) (xy 2.796235 0.512067) (xy 2.792498 0.556303) (xy 2.791029 0.583056) (xy 2.786885 0.645974)
|
||||
(xy 2.780020 0.720476) (xy 2.770903 0.803085) (xy 2.760003 0.890325) (xy 2.747790 0.978718) (xy 2.734731 1.064789) (xy 2.721296 1.145061) (xy 2.707953 1.216057) (xy 2.701481 1.246910)
|
||||
(xy 2.690900 1.303583) (xy 2.680718 1.374845) (xy 2.670990 1.459894) (xy 2.661769 1.557929) (xy 2.653111 1.668148) (xy 2.645069 1.789750) (xy 2.637696 1.921934) (xy 2.631048 2.063898)
|
||||
(xy 2.625178 2.214840) (xy 2.620140 2.373960) (xy 2.616863 2.501516) (xy 2.614307 2.605502) (xy 2.611774 2.695077) (xy 2.609206 2.771223) (xy 2.606544 2.834923) (xy 2.603730 2.887159)
|
||||
(xy 2.600706 2.928913) (xy 2.597413 2.961169) (xy 2.593794 2.984908) (xy 2.589789 3.001113) (xy 2.586769 3.008418) (xy 2.581178 3.014976) (xy 2.570957 3.020772) (xy 2.554674 3.026039)
|
||||
(xy 2.530895 3.031007) (xy 2.498186 3.035909) (xy 2.455114 3.040977) (xy 2.400245 3.046441) (xy 2.332146 3.052535) (xy 2.293697 3.055805) (xy 2.190547 3.064761) (xy 2.081487 3.074810)
|
||||
(xy 1.964788 3.086126) (xy 1.838724 3.098882) (xy 1.701567 3.113249) (xy 1.551591 3.129400) (xy 1.485515 3.136631) (xy 1.309180 3.155636) (xy 1.146197 3.172398) (xy 0.994709 3.187074)
|
||||
(xy 0.852862 3.199823) (xy 0.718801 3.210802) (xy 0.590671 3.220168) (xy 0.466617 3.228078) (xy 0.344785 3.234692) (xy 0.312626 3.236247) (xy 0.254556 3.239179) (xy 0.201459 3.242229)
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(xy 1.772207 -3.073740) (xy 1.733538 -3.072245) (xy 1.682988 -3.070359) (xy 1.622308 -3.068146) (xy 1.553252 -3.065668) (xy 1.477570 -3.062989) (xy 1.397014 -3.060171) (xy 1.313337 -3.057278)
|
||||
(xy 1.258786 -3.055410) (xy 0.812694 -3.040195) (xy 0.794932 -3.061415) (xy 0.763630 -3.105415) (xy 0.742689 -3.149234) (xy 0.735083 -3.178848) (xy 0.734188 -3.195589) (xy 0.734205 -3.225313)
|
||||
(xy 0.735065 -3.265640) (xy 0.735733 -3.285465) (xy 0.823576 -3.285465) (xy 0.828032 -3.241919) (xy 0.841901 -3.209577) (xy 0.865935 -3.186914) (xy 0.874583 -3.182099) (xy 0.883088 -3.178327)
|
||||
(xy 0.892983 -3.175227) (xy 0.905838 -3.172716) (xy 0.923220 -3.170713) (xy 0.946696 -3.169135) (xy 0.977835 -3.167899) (xy 1.018204 -3.166925) (xy 1.069371 -3.166129) (xy 1.132904 -3.165429)
|
||||
(xy 1.204576 -3.164791) (xy 1.490003 -3.165601) (xy 1.776652 -3.172662) (xy 2.061314 -3.185795) (xy 2.340782 -3.204820) (xy 2.611848 -3.229561) (xy 2.840182 -3.255828) (xy 2.891314 -3.262298)
|
||||
(xy 2.937329 -3.268068) (xy 2.976038 -3.272866) (xy 3.005248 -3.276424) (xy 3.022771 -3.278470) (xy 3.026833 -3.278861) (xy 3.029918 -3.274161) (xy 3.031462 -3.259568) (xy 3.031419 -3.234444)
|
||||
(xy 3.029741 -3.198145) (xy 3.026381 -3.150032) (xy 3.021294 -3.089464) (xy 3.014431 -3.015799) (xy 3.005745 -2.928396) (xy 2.995191 -2.826615) (xy 2.990512 -2.782454) (xy 2.987639 -2.749642)
|
||||
(xy 2.984543 -2.703979) (xy 2.981351 -2.648004) (xy 2.978189 -2.584258) (xy 2.975184 -2.515278) (xy 2.972461 -2.443605) (xy 2.970227 -2.374515) (xy 2.968197 -2.293637) (xy 2.966616 -2.205797)
|
||||
(xy 2.965466 -2.112157) (xy 2.964729 -2.013879) (xy 2.964387 -1.912126) (xy 2.964421 -1.808061) (xy 2.964815 -1.702847) (xy 2.965549 -1.597647) (xy 2.966606 -1.493622) (xy 2.967969 -1.391937)
|
||||
(xy 2.969618 -1.293754) (xy 2.971536 -1.200235) (xy 2.973706 -1.112543) (xy 2.976108 -1.031842) (xy 2.978726 -0.959293) (xy 2.981541 -0.896060) (xy 2.984535 -0.843306) (xy 2.987691 -0.802192)
|
||||
(xy 2.990989 -0.773883) (xy 2.994413 -0.759540) (xy 2.995207 -0.758348) (xy 3.003440 -0.757177) (xy 3.024992 -0.755516) (xy 3.057802 -0.753485) (xy 3.099805 -0.751203) (xy 3.148940 -0.748789)
|
||||
(xy 3.198297 -0.746572) (xy 3.252441 -0.744152) (xy 3.301610 -0.741782) (xy 3.343679 -0.739577) (xy 3.376525 -0.737655) (xy 3.398023 -0.736132) (xy 3.405909 -0.735199) (xy 3.417346 -0.732791)
|
||||
(xy 3.424593 -0.738147) (xy 3.430730 -0.754407) (xy 3.433084 -0.762875) (xy 3.441432 -0.796955) (xy 3.451759 -0.844104) (xy 3.463669 -0.902182) (xy 3.476763 -0.969050) (xy 3.490644 -1.042566)
|
||||
(xy 3.504913 -1.120593) (xy 3.519173 -1.200988) (xy 3.533026 -1.281613) (xy 3.546075 -1.360327) (xy 3.557402 -1.431636) (xy 3.565246 -1.495353) (xy 3.570829 -1.570937) (xy 3.574146 -1.658837)
|
||||
(xy 3.575197 -1.759504) (xy 3.573978 -1.873384) (xy 3.570486 -2.000928) (xy 3.564720 -2.142585) (xy 3.556677 -2.298803) (xy 3.552051 -2.378363) (xy 3.545127 -2.498841) (xy 3.539626 -2.607034)
|
||||
(xy 3.535437 -2.705975) (xy 3.532453 -2.798699) (xy 3.530565 -2.888238) (xy 3.529665 -2.977625) (xy 3.529569 -3.005666) (xy 3.529060 -3.267363) (xy 3.554921 -3.417454) (xy 3.563456 -3.469541)
|
||||
(xy 3.571265 -3.521944) (xy 3.577811 -3.570694) (xy 3.582558 -3.611824) (xy 3.584841 -3.638893) (xy 3.586066 -3.679477) (xy 3.583379 -3.707451) (xy 3.575387 -3.725393) (xy 3.560697 -3.735879)
|
||||
(xy 3.537916 -3.741486) (xy 3.528745 -3.742664) (xy 3.505039 -3.747122) (xy 3.486746 -3.753658) (xy 3.482883 -3.756117) (xy 3.472444 -3.773337) (xy 3.473638 -3.793322) (xy 3.485788 -3.809592)
|
||||
(xy 3.488651 -3.811388) (xy 3.498049 -3.817406) (xy 3.497156 -3.821146) (xy 3.484009 -3.824301) (xy 3.471333 -3.826326) (xy 3.444873 -3.829157) (xy 3.404059 -3.831835) (xy 3.349928 -3.834345)
|
||||
(xy 3.283519 -3.836673) (xy 3.205871 -3.838805) (xy 3.118022 -3.840726) (xy 3.021011 -3.842421) (xy 2.915876 -3.843877) (xy 2.803656 -3.845080) (xy 2.685389 -3.846013) (xy 2.562114 -3.846665)
|
||||
(xy 2.434869 -3.847019) (xy 2.304693 -3.847061) (xy 2.172624 -3.846778) (xy 2.039701 -3.846154) (xy 2.039697 -3.846154) (xy 1.914750 -3.845288) (xy 1.792699 -3.844215) (xy 1.674484 -3.842957)
|
||||
(xy 1.561043 -3.841532) (xy 1.453315 -3.839961) (xy 1.352241 -3.838264) (xy 1.258758 -3.836460) (xy 1.173806 -3.834570) (xy 1.098323 -3.832613) (xy 1.033250 -3.830609) (xy 0.979525 -3.828578)
|
||||
(xy 0.938088 -3.826539) (xy 0.909876 -3.824514) (xy 0.895830 -3.822521) (xy 0.894503 -3.821917) (xy 0.892426 -3.813444) (xy 0.888759 -3.791827) (xy 0.883786 -3.759202) (xy 0.877789 -3.717703)
|
||||
(xy 0.871049 -3.669468) (xy 0.863850 -3.616630) (xy 0.856474 -3.561326) (xy 0.849203 -3.505691) (xy 0.842319 -3.451861) (xy 0.836105 -3.401972) (xy 0.830843 -3.358159) (xy 0.826816 -3.322557)
|
||||
(xy 0.824306 -3.297303) (xy 0.823576 -3.285465) (xy 0.735733 -3.285465) (xy 0.736703 -3.314190) (xy 0.739049 -3.368584) (xy 0.742038 -3.426441) (xy 0.742181 -3.429000) (xy 0.745919 -3.496753)
|
||||
(xy 0.749834 -3.570070) (xy 0.753692 -3.644404) (xy 0.757260 -3.715209) (xy 0.760303 -3.777939) (xy 0.761789 -3.810000) (xy 0.764448 -3.860827) (xy 0.767596 -3.908115) (xy 0.770997 -3.949098)
|
||||
(xy 0.774413 -3.981012) (xy 0.777607 -4.001090) (xy 0.778441 -4.004251) (xy 0.795116 -4.039913) (xy 0.817967 -4.061480) (xy 0.847106 -4.069005) (xy 0.882644 -4.062544) )(layer F.SilkS) (width 0.010000)
|
||||
)
|
||||
)
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,3 @@
|
|||
(sym_lib_table
|
||||
(lib (name ttl-fpga-rescue)(type Legacy)(uri ${KIPRJMOD}/ttl-fpga-rescue.lib)(options "")(descr ""))
|
||||
)
|
|
@ -0,0 +1,438 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# 4xxx_4066
|
||||
#
|
||||
DEF 4xxx_4066 U 0 40 Y Y 5 L N
|
||||
F0 "U" -300 350 50 H V C CNN
|
||||
F1 "4xxx_4066" -300 -350 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS 4066
|
||||
$FPLIST
|
||||
DIP?14*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 300 200 -300 5 1 10 f
|
||||
P 2 1 0 6 0 50 0 100 N
|
||||
P 4 1 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 1 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
P 2 2 0 6 0 50 0 100 N
|
||||
P 4 2 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 2 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
P 2 3 0 6 0 50 0 100 N
|
||||
P 4 3 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 3 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
P 2 4 0 6 0 50 0 100 N
|
||||
P 4 4 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 4 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
X ~ 1 -300 0 200 R 50 50 1 0 P
|
||||
X ~ 13 0 300 200 D 50 50 1 0 I
|
||||
X ~ 2 300 0 200 L 50 50 1 0 P
|
||||
X ~ 3 300 0 200 L 50 50 2 0 P
|
||||
X ~ 4 -300 0 200 R 50 50 2 0 P
|
||||
X ~ 5 0 300 200 D 50 50 2 0 I
|
||||
X ~ 6 0 300 200 D 50 50 3 0 I
|
||||
X ~ 8 -300 0 200 R 50 50 3 0 P
|
||||
X ~ 9 300 0 200 L 50 50 3 0 P
|
||||
X ~ 10 300 0 200 L 50 50 4 0 P
|
||||
X ~ 11 -300 0 200 R 50 50 4 0 P
|
||||
X ~ 12 0 300 200 D 50 50 4 0 I
|
||||
X VDD 14 0 500 200 D 50 50 5 0 W
|
||||
X VSS 7 0 -500 200 U 50 50 5 0 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74xx_74LS174
|
||||
#
|
||||
DEF 74xx_74LS174 U 0 40 Y Y 1 L N
|
||||
F0 "U" -300 550 50 H V C CNN
|
||||
F1 "74xx_74LS174" -300 -650 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
DIP?16*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -300 500 300 -600 1 1 10 f
|
||||
X ~Mr 1 -500 -500 200 R 50 50 1 0 I
|
||||
X Q3 10 500 100 200 L 50 50 1 0 O
|
||||
X D3 11 -500 100 200 R 50 50 1 0 I
|
||||
X Q4 12 500 0 200 L 50 50 1 0 O
|
||||
X D4 13 -500 0 200 R 50 50 1 0 I
|
||||
X D5 14 -500 -100 200 R 50 50 1 0 I
|
||||
X Q5 15 500 -100 200 L 50 50 1 0 O
|
||||
X VCC 16 0 700 200 D 50 50 1 0 W
|
||||
X Q0 2 500 400 200 L 50 50 1 0 O
|
||||
X D0 3 -500 400 200 R 50 50 1 0 I
|
||||
X D1 4 -500 300 200 R 50 50 1 0 I
|
||||
X Q1 5 500 300 200 L 50 50 1 0 O
|
||||
X D2 6 -500 200 200 R 50 50 1 0 I
|
||||
X Q2 7 500 200 200 L 50 50 1 0 O
|
||||
X GND 8 0 -800 200 U 50 50 1 0 W
|
||||
X Cp 9 -500 -300 200 R 50 50 1 0 I C
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74xx_IEEE_74157
|
||||
#
|
||||
DEF 74xx_IEEE_74157 U 0 30 Y Y 1 F N
|
||||
F0 "U" 300 400 50 H V C CNN
|
||||
F1 "74xx_IEEE_74157" 250 -650 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 0 100 60 0 0 0 MUX Normal 0 C C
|
||||
S -250 -400 250 -600 0 0 0 N
|
||||
S -250 -200 250 -400 0 0 0 N
|
||||
S -250 0 250 -200 0 0 0 N
|
||||
S -250 200 250 0 0 0 0 N
|
||||
P 9 0 0 0 -200 200 -200 250 -250 250 -250 500 250 500 250 250 200 250 200 200 200 200 N
|
||||
X VCC 16 150 500 0 D 50 50 0 0 W N
|
||||
X GND 8 0 500 0 D 50 50 0 0 W N
|
||||
X A/B 1 -550 300 300 R 50 50 1 1 I
|
||||
X I1d 10 -550 -550 300 R 50 50 1 1 I
|
||||
X I0d 11 -550 -450 300 R 50 50 1 1 I
|
||||
X Qc 12 550 -300 300 L 50 50 1 1 O
|
||||
X I1c 13 -550 -350 300 R 50 50 1 1 I
|
||||
X I0c 14 -550 -250 300 R 50 50 1 1 I
|
||||
X ~EN 15 -550 400 300 R 50 50 1 1 I I
|
||||
X I0a 2 -550 150 300 R 50 50 1 1 I
|
||||
X I1a 3 -550 50 300 R 50 50 1 1 I
|
||||
X Qa 4 550 100 300 L 50 50 1 1 O
|
||||
X I0b 5 -550 -50 300 R 50 50 1 1 I
|
||||
X I1b 6 -550 -150 300 R 50 50 1 1 I
|
||||
X Qb 7 550 -100 300 L 50 50 1 1 O
|
||||
X Qd 9 550 -500 300 L 50 50 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74xx_IEEE_74164
|
||||
#
|
||||
DEF 74xx_IEEE_74164 U 0 30 Y Y 1 F N
|
||||
F0 "U" 350 250 50 H V C CNN
|
||||
F1 "74xx_IEEE_74164" 250 -900 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 -170 -40 60 0 0 0 & Normal 0 C C
|
||||
S -250 -750 250 -850 0 1 0 N
|
||||
S -250 -650 250 -750 0 1 0 N
|
||||
S -250 -550 250 -650 0 1 0 N
|
||||
S -250 -450 250 -550 0 1 0 N
|
||||
S -250 -350 250 -450 0 1 0 N
|
||||
S -250 -250 250 -350 0 1 0 N
|
||||
S -250 -150 250 -250 0 1 0 N
|
||||
S -250 50 250 -150 0 1 0 N
|
||||
P 3 0 1 0 -100 50 -100 -150 -100 -150 N
|
||||
P 9 0 1 0 -200 50 -200 100 -250 100 -250 350 250 350 250 100 200 100 200 50 200 50 N
|
||||
X A 1 -550 0 300 R 50 50 1 1 I
|
||||
X Qe 10 550 -500 300 L 50 50 1 1 O
|
||||
X Qf 11 550 -600 300 L 50 50 1 1 O
|
||||
X Qg 12 550 -700 300 L 50 50 1 1 O
|
||||
X Qh 13 550 -800 300 L 50 50 1 1 O
|
||||
X Vdd 14 200 350 0 D 50 50 1 1 W N
|
||||
X B 2 -550 -100 300 R 50 50 1 1 I
|
||||
X Qa 3 550 -50 300 L 50 50 1 1 O
|
||||
X Qb 4 550 -200 300 L 50 50 1 1 O
|
||||
X Qc 5 550 -300 300 L 50 50 1 1 O
|
||||
X Qd 6 550 -400 300 L 50 50 1 1 O
|
||||
X Vss 7 0 350 0 D 50 50 1 1 W N
|
||||
X CK 8 -550 150 300 R 50 50 1 1 I C
|
||||
X ~R 9 -550 250 300 R 50 50 1 1 I I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74xx_IEEE_74251
|
||||
#
|
||||
DEF 74xx_IEEE_74251 U 0 30 Y Y 1 F N
|
||||
F0 "U" 300 600 50 H V C CNN
|
||||
F1 "74xx_IEEE_74251" 350 -800 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 0 250 50 0 0 0 MUX Normal 0 C C
|
||||
S -250 650 250 -700 0 0 0 N
|
||||
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
|
||||
P 5 0 0 0 80 380 20 380 50 320 80 380 80 380 N
|
||||
X VCC 16 0 650 0 D 50 50 0 0 W N
|
||||
X GND 8 0 -700 0 U 50 50 0 0 W N
|
||||
X I3 1 -550 -200 300 R 50 50 1 1 I
|
||||
X S1 10 -550 350 300 R 50 50 1 1 I
|
||||
X S0 11 -550 450 300 R 50 50 1 1 I
|
||||
X I7 12 -550 -600 300 R 50 50 1 1 I
|
||||
X I6 13 -550 -500 300 R 50 50 1 1 I
|
||||
X I5 14 -550 -400 300 R 50 50 1 1 I
|
||||
X I4 15 -550 -300 300 R 50 50 1 1 I
|
||||
X I2 2 -550 -100 300 R 50 50 1 1 I
|
||||
X I1 3 -550 0 300 R 50 50 1 1 I
|
||||
X I0 4 -550 100 300 R 50 50 1 1 I
|
||||
X Q 5 550 350 300 L 50 50 1 1 T
|
||||
X ~Q 6 550 -350 300 L 50 50 1 1 T I
|
||||
X ~E 7 -550 550 300 R 50 50 1 1 I I
|
||||
X S2 9 -550 250 300 R 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74xx_IEEE_74253
|
||||
#
|
||||
DEF 74xx_IEEE_74253 U 0 30 Y Y 1 F N
|
||||
F0 "U" 300 650 50 H V C CNN
|
||||
F1 "74xx_IEEE_74253" 150 -650 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 0 300 60 0 0 0 MUX Normal 0 C C
|
||||
S -250 -100 250 -600 0 0 0 N
|
||||
S -250 450 250 -100 0 0 0 N
|
||||
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
|
||||
P 5 0 0 0 80 180 20 180 50 120 80 180 80 180 N
|
||||
P 9 0 0 0 -200 450 -200 500 -250 500 -250 750 250 750 250 500 200 500 200 450 200 450 N
|
||||
X VCC 16 150 750 0 D 50 50 0 0 W N
|
||||
X GND 8 0 750 0 D 50 50 0 0 W N
|
||||
X ~ENa 1 -550 350 300 R 50 50 1 1 I I
|
||||
X I0b 10 -550 -250 300 R 50 50 1 1 I
|
||||
X I1b 11 -550 -350 300 R 50 50 1 1 I
|
||||
X I2b 12 -550 -450 300 R 50 50 1 1 I
|
||||
X I3b 13 -550 -550 300 R 50 50 1 1 I
|
||||
X A 14 -550 650 300 R 50 50 1 1 I
|
||||
X ~ENb 15 -550 -150 300 R 50 50 1 1 I I
|
||||
X B 2 -550 550 300 R 50 50 1 1 I
|
||||
X I3a 3 -550 -50 300 R 50 50 1 1 I
|
||||
X I2a 4 -550 50 300 R 50 50 1 1 I
|
||||
X I1a 5 -550 150 300 R 50 50 1 1 I
|
||||
X I0a 6 -550 250 300 R 50 50 1 1 I
|
||||
X Qa 7 550 150 300 L 50 50 1 1 T
|
||||
X Qb 9 550 -350 300 L 50 50 1 1 T
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Connector_Conn_01x12_Female
|
||||
#
|
||||
DEF Connector_Conn_01x12_Female J 0 40 Y N 1 F N
|
||||
F0 "J" 0 600 50 H V C CNN
|
||||
F1 "Connector_Conn_01x12_Female" 0 -700 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Connector*:*_1x??_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
A 0 -600 20 901 -901 1 1 6 N 0 -580 0 -620
|
||||
A 0 -500 20 901 -901 1 1 6 N 0 -480 0 -520
|
||||
A 0 -400 20 901 -901 1 1 6 N 0 -380 0 -420
|
||||
A 0 -300 20 901 -901 1 1 6 N 0 -280 0 -320
|
||||
A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220
|
||||
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
|
||||
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
|
||||
A 0 100 20 901 -901 1 1 6 N 0 120 0 80
|
||||
A 0 200 20 901 -901 1 1 6 N 0 220 0 180
|
||||
A 0 300 20 901 -901 1 1 6 N 0 320 0 280
|
||||
A 0 400 20 901 -901 1 1 6 N 0 420 0 380
|
||||
A 0 500 20 901 -901 1 1 6 N 0 520 0 480
|
||||
P 2 1 1 6 -50 -600 -20 -600 N
|
||||
P 2 1 1 6 -50 -500 -20 -500 N
|
||||
P 2 1 1 6 -50 -400 -20 -400 N
|
||||
P 2 1 1 6 -50 -300 -20 -300 N
|
||||
P 2 1 1 6 -50 -200 -20 -200 N
|
||||
P 2 1 1 6 -50 -100 -20 -100 N
|
||||
P 2 1 1 6 -50 0 -20 0 N
|
||||
P 2 1 1 6 -50 100 -20 100 N
|
||||
P 2 1 1 6 -50 200 -20 200 N
|
||||
P 2 1 1 6 -50 300 -20 300 N
|
||||
P 2 1 1 6 -50 400 -20 400 N
|
||||
P 2 1 1 6 -50 500 -20 500 N
|
||||
X Pin_1 1 -200 500 150 R 50 50 1 1 P
|
||||
X Pin_10 10 -200 -400 150 R 50 50 1 1 P
|
||||
X Pin_11 11 -200 -500 150 R 50 50 1 1 P
|
||||
X Pin_12 12 -200 -600 150 R 50 50 1 1 P
|
||||
X Pin_2 2 -200 400 150 R 50 50 1 1 P
|
||||
X Pin_3 3 -200 300 150 R 50 50 1 1 P
|
||||
X Pin_4 4 -200 200 150 R 50 50 1 1 P
|
||||
X Pin_5 5 -200 100 150 R 50 50 1 1 P
|
||||
X Pin_6 6 -200 0 150 R 50 50 1 1 P
|
||||
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
|
||||
X Pin_8 8 -200 -200 150 R 50 50 1 1 P
|
||||
X Pin_9 9 -200 -300 150 R 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Connector_Conn_01x12_Male
|
||||
#
|
||||
DEF Connector_Conn_01x12_Male J 0 40 Y N 1 F N
|
||||
F0 "J" 0 600 50 H V C CNN
|
||||
F1 "Connector_Conn_01x12_Male" 0 -700 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Connector*:*_1x??_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S 34 -595 0 -605 1 1 6 F
|
||||
S 34 -495 0 -505 1 1 6 F
|
||||
S 34 -395 0 -405 1 1 6 F
|
||||
S 34 -295 0 -305 1 1 6 F
|
||||
S 34 -195 0 -205 1 1 6 F
|
||||
S 34 -95 0 -105 1 1 6 F
|
||||
S 34 5 0 -5 1 1 6 F
|
||||
S 34 105 0 95 1 1 6 F
|
||||
S 34 205 0 195 1 1 6 F
|
||||
S 34 305 0 295 1 1 6 F
|
||||
S 34 405 0 395 1 1 6 F
|
||||
S 34 505 0 495 1 1 6 F
|
||||
P 2 1 1 6 50 -600 34 -600 N
|
||||
P 2 1 1 6 50 -500 34 -500 N
|
||||
P 2 1 1 6 50 -400 34 -400 N
|
||||
P 2 1 1 6 50 -300 34 -300 N
|
||||
P 2 1 1 6 50 -200 34 -200 N
|
||||
P 2 1 1 6 50 -100 34 -100 N
|
||||
P 2 1 1 6 50 0 34 0 N
|
||||
P 2 1 1 6 50 100 34 100 N
|
||||
P 2 1 1 6 50 200 34 200 N
|
||||
P 2 1 1 6 50 300 34 300 N
|
||||
P 2 1 1 6 50 400 34 400 N
|
||||
P 2 1 1 6 50 500 34 500 N
|
||||
X Pin_1 1 200 500 150 L 50 50 1 1 P
|
||||
X Pin_10 10 200 -400 150 L 50 50 1 1 P
|
||||
X Pin_11 11 200 -500 150 L 50 50 1 1 P
|
||||
X Pin_12 12 200 -600 150 L 50 50 1 1 P
|
||||
X Pin_2 2 200 400 150 L 50 50 1 1 P
|
||||
X Pin_3 3 200 300 150 L 50 50 1 1 P
|
||||
X Pin_4 4 200 200 150 L 50 50 1 1 P
|
||||
X Pin_5 5 200 100 150 L 50 50 1 1 P
|
||||
X Pin_6 6 200 0 150 L 50 50 1 1 P
|
||||
X Pin_7 7 200 -100 150 L 50 50 1 1 P
|
||||
X Pin_8 8 200 -200 150 L 50 50 1 1 P
|
||||
X Pin_9 9 200 -300 150 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_C
|
||||
#
|
||||
DEF Device_C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
C_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 20 -80 -30 80 -30 N
|
||||
P 2 0 1 20 -80 30 80 30 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_CP
|
||||
#
|
||||
DEF Device_CP C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_CP" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
CP_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -90 20 90 40 0 1 0 N
|
||||
S 90 -20 -90 -40 0 1 0 F
|
||||
P 2 0 1 0 -70 90 -30 90 N
|
||||
P 2 0 1 0 -50 110 -50 70 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_D_Schottky
|
||||
#
|
||||
DEF Device_D_Schottky D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "Device_D_Schottky" 0 -100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
TO-???*
|
||||
*_Diode_*
|
||||
*SingleDiode*
|
||||
D_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 0 50 0 -50 0 N
|
||||
P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
|
||||
P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
|
||||
X K 1 -150 0 100 R 50 50 1 1 P
|
||||
X A 2 150 0 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_LED
|
||||
#
|
||||
DEF Device_LED D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "Device_LED" 0 -100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
LED*
|
||||
LED_SMD:*
|
||||
LED_THT:*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 8 -50 -50 -50 50 N
|
||||
P 2 0 1 0 -50 0 50 0 N
|
||||
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
|
||||
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
|
||||
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
|
||||
X K 1 -150 0 100 R 50 50 1 1 P
|
||||
X A 2 150 0 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_R
|
||||
#
|
||||
DEF Device_R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "Device_R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GNDD
|
||||
#
|
||||
DEF power_GNDD #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GNDD" 0 -125 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -50 -60 50 -80 0 1 10 F
|
||||
P 2 0 1 0 0 0 0 -60 N
|
||||
X GNDD 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_VCC
|
||||
#
|
||||
DEF power_VCC #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_VCC" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
C 0 75 25 0 1 0 N
|
||||
P 2 0 1 0 0 0 0 50 N
|
||||
X VCC 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
|
@ -0,0 +1,3 @@
|
|||
EESchema-DOCLIB Version 2.0
|
||||
#
|
||||
#End Doc Library
|
|
@ -0,0 +1,236 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# 4066-4xxx
|
||||
#
|
||||
DEF 4066-4xxx U 0 40 Y Y 5 L N
|
||||
F0 "U" -300 350 50 H V C CNN
|
||||
F1 "4066-4xxx" -300 -350 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
DIP?14*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 300 200 -300 5 1 10 f
|
||||
P 2 1 0 6 0 50 0 100 N
|
||||
P 4 1 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 1 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
P 2 2 0 6 0 50 0 100 N
|
||||
P 4 2 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 2 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
P 2 3 0 6 0 50 0 100 N
|
||||
P 4 3 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 3 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
P 2 4 0 6 0 50 0 100 N
|
||||
P 4 4 0 0 -100 0 100 100 100 -100 -100 0 f
|
||||
P 4 4 0 0 -100 100 100 0 -100 -100 -100 100 f
|
||||
X ~ 1 -300 0 200 R 50 50 1 0 P
|
||||
X ~ 13 0 300 200 D 50 50 1 0 I
|
||||
X ~ 2 300 0 200 L 50 50 1 0 P
|
||||
X ~ 3 300 0 200 L 50 50 2 0 P
|
||||
X ~ 4 -300 0 200 R 50 50 2 0 P
|
||||
X ~ 5 0 300 200 D 50 50 2 0 I
|
||||
X ~ 6 0 300 200 D 50 50 3 0 I
|
||||
X ~ 8 -300 0 200 R 50 50 3 0 P
|
||||
X ~ 9 300 0 200 L 50 50 3 0 P
|
||||
X ~ 10 300 0 200 L 50 50 4 0 P
|
||||
X ~ 11 -300 0 200 R 50 50 4 0 P
|
||||
X ~ 12 0 300 200 D 50 50 4 0 I
|
||||
X VDD 14 0 500 200 D 50 50 5 0 W
|
||||
X VSS 7 0 -500 200 U 50 50 5 0 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74157-74xx_IEEE
|
||||
#
|
||||
DEF 74157-74xx_IEEE U 0 30 Y Y 1 F N
|
||||
F0 "U" 300 400 50 H V C CNN
|
||||
F1 "74157-74xx_IEEE" 250 -650 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 0 100 60 0 0 0 MUX Normal 0 C C
|
||||
S -250 -400 250 -600 0 0 0 N
|
||||
S -250 -200 250 -400 0 0 0 N
|
||||
S -250 0 250 -200 0 0 0 N
|
||||
S -250 200 250 0 0 0 0 N
|
||||
P 9 0 0 0 -200 200 -200 250 -250 250 -250 500 250 500 250 250 200 250 200 200 200 200 N
|
||||
X VCC 16 150 500 0 D 50 50 0 0 W N
|
||||
X GND 8 0 500 0 D 50 50 0 0 W N
|
||||
X A/B 1 -550 300 300 R 50 50 1 1 I
|
||||
X I1d 10 -550 -550 300 R 50 50 1 1 I
|
||||
X I0d 11 -550 -450 300 R 50 50 1 1 I
|
||||
X Qc 12 550 -300 300 L 50 50 1 1 O
|
||||
X I1c 13 -550 -350 300 R 50 50 1 1 I
|
||||
X I0c 14 -550 -250 300 R 50 50 1 1 I
|
||||
X ~EN 15 -550 400 300 R 50 50 1 1 I I
|
||||
X I0a 2 -550 150 300 R 50 50 1 1 I
|
||||
X I1a 3 -550 50 300 R 50 50 1 1 I
|
||||
X Qa 4 550 100 300 L 50 50 1 1 O
|
||||
X I0b 5 -550 -50 300 R 50 50 1 1 I
|
||||
X I1b 6 -550 -150 300 R 50 50 1 1 I
|
||||
X Qb 7 550 -100 300 L 50 50 1 1 O
|
||||
X Qd 9 550 -500 300 L 50 50 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74164-74xx_IEEE
|
||||
#
|
||||
DEF 74164-74xx_IEEE U 0 30 Y Y 1 F N
|
||||
F0 "U" 350 250 50 H V C CNN
|
||||
F1 "74164-74xx_IEEE" 250 -900 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 -170 -40 60 0 0 0 & Normal 0 C C
|
||||
S -250 -750 250 -850 0 1 0 N
|
||||
S -250 -650 250 -750 0 1 0 N
|
||||
S -250 -550 250 -650 0 1 0 N
|
||||
S -250 -450 250 -550 0 1 0 N
|
||||
S -250 -350 250 -450 0 1 0 N
|
||||
S -250 -250 250 -350 0 1 0 N
|
||||
S -250 -150 250 -250 0 1 0 N
|
||||
S -250 50 250 -150 0 1 0 N
|
||||
P 3 0 1 0 -100 50 -100 -150 -100 -150 N
|
||||
P 9 0 1 0 -200 50 -200 100 -250 100 -250 350 250 350 250 100 200 100 200 50 200 50 N
|
||||
X A 1 -550 0 300 R 50 50 1 1 I
|
||||
X Qe 10 550 -500 300 L 50 50 1 1 O
|
||||
X Qf 11 550 -600 300 L 50 50 1 1 O
|
||||
X Qg 12 550 -700 300 L 50 50 1 1 O
|
||||
X Qh 13 550 -800 300 L 50 50 1 1 O
|
||||
X Vdd 14 200 350 0 D 50 50 1 1 W N
|
||||
X B 2 -550 -100 300 R 50 50 1 1 I
|
||||
X Qa 3 550 -50 300 L 50 50 1 1 O
|
||||
X Qb 4 550 -200 300 L 50 50 1 1 O
|
||||
X Qc 5 550 -300 300 L 50 50 1 1 O
|
||||
X Qd 6 550 -400 300 L 50 50 1 1 O
|
||||
X Vss 7 0 350 0 D 50 50 1 1 W N
|
||||
X CK 8 -550 150 300 R 50 50 1 1 I C
|
||||
X ~R 9 -550 250 300 R 50 50 1 1 I I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74251-74xx_IEEE
|
||||
#
|
||||
DEF 74251-74xx_IEEE U 0 30 Y Y 1 F N
|
||||
F0 "U" 300 600 50 H V C CNN
|
||||
F1 "74251-74xx_IEEE" 350 -800 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 0 250 50 0 0 0 MUX Normal 0 C C
|
||||
S -250 650 250 -700 0 0 0 N
|
||||
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
|
||||
P 5 0 0 0 80 380 20 380 50 320 80 380 80 380 N
|
||||
X VCC 16 0 650 0 D 50 50 0 0 W N
|
||||
X GND 8 0 -700 0 U 50 50 0 0 W N
|
||||
X I3 1 -550 -200 300 R 50 50 1 1 I
|
||||
X S1 10 -550 350 300 R 50 50 1 1 I
|
||||
X S0 11 -550 450 300 R 50 50 1 1 I
|
||||
X I7 12 -550 -600 300 R 50 50 1 1 I
|
||||
X I6 13 -550 -500 300 R 50 50 1 1 I
|
||||
X I5 14 -550 -400 300 R 50 50 1 1 I
|
||||
X I4 15 -550 -300 300 R 50 50 1 1 I
|
||||
X I2 2 -550 -100 300 R 50 50 1 1 I
|
||||
X I1 3 -550 0 300 R 50 50 1 1 I
|
||||
X I0 4 -550 100 300 R 50 50 1 1 I
|
||||
X Q 5 550 350 300 L 50 50 1 1 T
|
||||
X ~Q 6 550 -350 300 L 50 50 1 1 T I
|
||||
X ~E 7 -550 550 300 R 50 50 1 1 I I
|
||||
X S2 9 -550 250 300 R 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# 74253-74xx_IEEE
|
||||
#
|
||||
DEF 74253-74xx_IEEE U 0 30 Y Y 1 F N
|
||||
F0 "U" 300 650 50 H V C CNN
|
||||
F1 "74253-74xx_IEEE" 150 -650 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
T 0 0 300 60 0 0 0 MUX Normal 0 C C
|
||||
S -250 -100 250 -600 0 0 0 N
|
||||
S -250 450 250 -100 0 0 0 N
|
||||
P 5 0 0 0 80 -320 20 -320 50 -380 80 -320 80 -320 N
|
||||
P 5 0 0 0 80 180 20 180 50 120 80 180 80 180 N
|
||||
P 9 0 0 0 -200 450 -200 500 -250 500 -250 750 250 750 250 500 200 500 200 450 200 450 N
|
||||
X VCC 16 150 750 0 D 50 50 0 0 W N
|
||||
X GND 8 0 750 0 D 50 50 0 0 W N
|
||||
X ~ENa 1 -550 350 300 R 50 50 1 1 I I
|
||||
X I0b 10 -550 -250 300 R 50 50 1 1 I
|
||||
X I1b 11 -550 -350 300 R 50 50 1 1 I
|
||||
X I2b 12 -550 -450 300 R 50 50 1 1 I
|
||||
X I3b 13 -550 -550 300 R 50 50 1 1 I
|
||||
X A 14 -550 650 300 R 50 50 1 1 I
|
||||
X ~ENb 15 -550 -150 300 R 50 50 1 1 I I
|
||||
X B 2 -550 550 300 R 50 50 1 1 I
|
||||
X I3a 3 -550 -50 300 R 50 50 1 1 I
|
||||
X I2a 4 -550 50 300 R 50 50 1 1 I
|
||||
X I1a 5 -550 150 300 R 50 50 1 1 I
|
||||
X I0a 6 -550 250 300 R 50 50 1 1 I
|
||||
X Qa 7 550 150 300 L 50 50 1 1 T
|
||||
X Qb 9 550 -350 300 L 50 50 1 1 T
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# D_ALT-Device
|
||||
#
|
||||
DEF D_ALT-Device D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "D_ALT-Device" 0 -100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
TO-???*
|
||||
*_Diode_*
|
||||
*SingleDiode*
|
||||
D_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 8 -50 50 -50 -50 N
|
||||
P 2 0 1 0 50 0 -50 0 N
|
||||
P 4 0 1 8 50 50 50 -50 -50 0 50 50 F
|
||||
X K 1 -150 0 100 R 50 50 1 1 P
|
||||
X A 2 150 0 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Q_NPN_BCE-Device
|
||||
#
|
||||
DEF Q_NPN_BCE-Device Q 0 0 Y N 1 F N
|
||||
F0 "Q" 200 50 50 H V L CNN
|
||||
F1 "Q_NPN_BCE-Device" 200 -50 50 H V L CNN
|
||||
F2 "" 200 100 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
C 50 0 111 0 1 10 N
|
||||
P 2 0 1 0 25 25 100 100 N
|
||||
P 3 0 1 0 25 -25 100 -100 100 -100 N
|
||||
P 3 0 1 20 25 75 25 -75 25 -75 N
|
||||
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
|
||||
X B 1 -200 0 225 R 50 50 1 1 I
|
||||
X C 2 100 200 100 D 50 50 1 1 P
|
||||
X E 3 100 -200 100 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# R-Device
|
||||
#
|
||||
DEF R-Device R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "R-Device" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,241 @@
|
|||
update=Tue 11 Jun 2019 09:23:50 PM CEST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=ttl-fpga.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.1524
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.1524
|
||||
TrackWidth2=0.3
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
ViaDiameter2=0.8
|
||||
ViaDrill2=0.4
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.051
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.1524
|
||||
TrackWidth=0.1524
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
|
@ -0,0 +1,609 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:ttl-fpga-cache
|
||||
EELAYER 29 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 3
|
||||
Title "DISCRETE TTL FPGA"
|
||||
Date "2019-05-31"
|
||||
Rev "02L"
|
||||
Comp "Markus Koch <markus@notsyncing.net>"
|
||||
Comment1 "PCB"
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
8000 3350 7900 3350
|
||||
Wire Wire Line
|
||||
7900 3350 7900 3250
|
||||
$Comp
|
||||
L power:VCC #PWR04
|
||||
U 1 1 5FF9C392
|
||||
P 7900 3250
|
||||
F 0 "#PWR04" H 7900 3100 50 0001 C CNN
|
||||
F 1 "VCC" H 7917 3423 50 0000 C CNN
|
||||
F 2 "" H 7900 3250 50 0001 C CNN
|
||||
F 3 "" H 7900 3250 50 0001 C CNN
|
||||
1 7900 3250
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDD #PWR06
|
||||
U 1 1 5FF9C39C
|
||||
P 7800 3450
|
||||
F 0 "#PWR06" H 7800 3200 50 0001 C CNN
|
||||
F 1 "GNDD" V 7804 3340 50 0000 R CNN
|
||||
F 2 "" H 7800 3450 50 0001 C CNN
|
||||
F 3 "" H 7800 3450 50 0001 C CNN
|
||||
1 7800 3450
|
||||
0 1 -1 0
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
7800 3450 8000 3450
|
||||
Wire Wire Line
|
||||
7200 3750 7200 3300
|
||||
Wire Wire Line
|
||||
8000 3750 7200 3750
|
||||
Wire Wire Line
|
||||
7300 3650 7300 3100
|
||||
Wire Wire Line
|
||||
8000 3650 7300 3650
|
||||
Wire Wire Line
|
||||
7400 3550 7400 3000
|
||||
Wire Wire Line
|
||||
8000 3550 7400 3550
|
||||
Text Label 7550 4150 0 50 ~ 0
|
||||
fabric_r3
|
||||
Text Label 7550 4250 0 50 ~ 0
|
||||
fabric_r2
|
||||
Text Label 7550 4350 0 50 ~ 0
|
||||
fabric_r1
|
||||
Text Label 7550 4450 0 50 ~ 0
|
||||
fabric_r0
|
||||
Wire Wire Line
|
||||
8000 4350 7550 4350
|
||||
Wire Wire Line
|
||||
8000 4250 7550 4250
|
||||
Wire Wire Line
|
||||
8000 4150 7550 4150
|
||||
Entry Wire Line
|
||||
7550 4350 7450 4450
|
||||
Entry Wire Line
|
||||
7550 4250 7450 4350
|
||||
Entry Wire Line
|
||||
7550 4150 7450 4250
|
||||
Entry Wire Line
|
||||
7550 4450 7450 4550
|
||||
Wire Bus Line
|
||||
7450 4550 6800 4550
|
||||
Wire Wire Line
|
||||
4450 3300 4450 3250
|
||||
Wire Wire Line
|
||||
5000 3250 5000 3300
|
||||
Wire Wire Line
|
||||
5000 3300 5650 3300
|
||||
Wire Wire Line
|
||||
4450 3250 5000 3250
|
||||
Connection ~ 4450 3300
|
||||
Wire Wire Line
|
||||
4450 3300 4550 3300
|
||||
Wire Wire Line
|
||||
4450 3100 4450 3050
|
||||
Wire Wire Line
|
||||
4450 3050 5000 3050
|
||||
Wire Wire Line
|
||||
5000 3050 5000 3100
|
||||
Wire Wire Line
|
||||
5000 3100 5550 3100
|
||||
Connection ~ 4450 3100
|
||||
Wire Wire Line
|
||||
4450 3100 4550 3100
|
||||
Wire Wire Line
|
||||
4950 3000 4950 2950
|
||||
Wire Wire Line
|
||||
4950 2950 4450 2950
|
||||
Wire Wire Line
|
||||
4950 3000 5450 3000
|
||||
Wire Wire Line
|
||||
4450 3000 4550 3000
|
||||
Wire Wire Line
|
||||
4450 2950 4450 3000
|
||||
Connection ~ 4450 3000
|
||||
Wire Wire Line
|
||||
4200 3400 4300 3400
|
||||
Wire Wire Line
|
||||
3900 3000 4450 3000
|
||||
Wire Wire Line
|
||||
4000 3100 4450 3100
|
||||
Wire Wire Line
|
||||
4100 3300 4450 3300
|
||||
Entry Wire Line
|
||||
3900 4250 3800 4150
|
||||
Entry Wire Line
|
||||
3900 4550 3800 4450
|
||||
Entry Wire Line
|
||||
3900 4450 3800 4350
|
||||
Entry Wire Line
|
||||
3900 4350 3800 4250
|
||||
Wire Wire Line
|
||||
3350 4150 3800 4150
|
||||
Wire Wire Line
|
||||
3350 4250 3800 4250
|
||||
Wire Wire Line
|
||||
3350 4350 3800 4350
|
||||
Wire Wire Line
|
||||
3350 4450 3800 4450
|
||||
Text Label 3800 4450 2 50 ~ 0
|
||||
fabric_l0
|
||||
Text Label 3800 4350 2 50 ~ 0
|
||||
fabric_l1
|
||||
Text Label 3800 4250 2 50 ~ 0
|
||||
fabric_l2
|
||||
Text Label 3800 4150 2 50 ~ 0
|
||||
fabric_l3
|
||||
Wire Wire Line
|
||||
3350 3550 3900 3550
|
||||
Wire Wire Line
|
||||
3900 3550 3900 3000
|
||||
Wire Wire Line
|
||||
3350 3650 4000 3650
|
||||
Wire Wire Line
|
||||
4000 3650 4000 3100
|
||||
Wire Wire Line
|
||||
3350 3750 4100 3750
|
||||
Wire Wire Line
|
||||
4100 3750 4100 3300
|
||||
Wire Wire Line
|
||||
3350 3850 4200 3850
|
||||
Wire Wire Line
|
||||
4200 3850 4200 3400
|
||||
Wire Wire Line
|
||||
3550 3450 3350 3450
|
||||
$Comp
|
||||
L power:GNDD #PWR05
|
||||
U 1 1 5FE8BD0F
|
||||
P 3550 3450
|
||||
F 0 "#PWR05" H 3550 3200 50 0001 C CNN
|
||||
F 1 "GNDD" V 3554 3340 50 0000 R CNN
|
||||
F 2 "" H 3550 3450 50 0001 C CNN
|
||||
F 3 "" H 3550 3450 50 0001 C CNN
|
||||
1 3550 3450
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:VCC #PWR03
|
||||
U 1 1 5FE8B843
|
||||
P 3450 3250
|
||||
F 0 "#PWR03" H 3450 3100 50 0001 C CNN
|
||||
F 1 "VCC" H 3467 3423 50 0000 C CNN
|
||||
F 2 "" H 3450 3250 50 0001 C CNN
|
||||
F 3 "" H 3450 3250 50 0001 C CNN
|
||||
1 3450 3250
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3450 3350 3450 3250
|
||||
Wire Wire Line
|
||||
3350 3350 3450 3350
|
||||
Wire Wire Line
|
||||
6800 3400 7100 3400
|
||||
Text Label 3950 4550 0 50 ~ 0
|
||||
fabric_l[3..0]
|
||||
Wire Wire Line
|
||||
7100 3400 7100 3850
|
||||
Wire Wire Line
|
||||
7100 3850 8000 3850
|
||||
Wire Wire Line
|
||||
3350 3950 8000 3950
|
||||
Text Notes 3100 4500 2 63 ~ 0
|
||||
VCC\nGND\nCLK\nRST\nSCK\nMOSI\nMISO\nMOSI_D\nI3\nI2\nI1\nI0
|
||||
Text Notes 8250 4500 0 63 ~ 0
|
||||
VCC\nGND\nCLK\nRST\nSCK\nmiso\nmosi\n\nI3\nI2\nI1\nI0
|
||||
Wire Wire Line
|
||||
5250 5600 5250 5550
|
||||
$Comp
|
||||
L power:VCC #PWR012
|
||||
U 1 1 60046AFF
|
||||
P 5250 5550
|
||||
F 0 "#PWR012" H 5250 5400 50 0001 C CNN
|
||||
F 1 "VCC" H 5150 5650 50 0000 C CNN
|
||||
F 2 "" H 5250 5550 50 0001 C CNN
|
||||
F 3 "" H 5250 5550 50 0001 C CNN
|
||||
1 5250 5550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GNDD #PWR09
|
||||
U 1 1 60046AF5
|
||||
P 5200 5200
|
||||
F 0 "#PWR09" H 5200 4950 50 0001 C CNN
|
||||
F 1 "GNDD" H 5204 5045 50 0000 C CNN
|
||||
F 2 "" H 5200 5200 50 0001 C CNN
|
||||
F 3 "" H 5200 5200 50 0001 C CNN
|
||||
1 5200 5200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5200 5150 5350 5150
|
||||
Wire Wire Line
|
||||
5350 5150 5350 5600
|
||||
Text Label 6050 5150 3 50 ~ 0
|
||||
fabric_b3
|
||||
Text Label 6150 5150 3 50 ~ 0
|
||||
fabric_b2
|
||||
Text Label 6250 5150 3 50 ~ 0
|
||||
fabric_b1
|
||||
Text Label 6350 5150 3 50 ~ 0
|
||||
fabric_b0
|
||||
Wire Wire Line
|
||||
6350 5600 6350 5150
|
||||
Wire Wire Line
|
||||
6250 5600 6250 5150
|
||||
Wire Wire Line
|
||||
6150 5600 6150 5150
|
||||
Wire Wire Line
|
||||
6050 5600 6050 5150
|
||||
Entry Wire Line
|
||||
6250 5150 6350 5050
|
||||
Entry Wire Line
|
||||
6150 5150 6250 5050
|
||||
Entry Wire Line
|
||||
6050 5150 6150 5050
|
||||
Entry Wire Line
|
||||
6350 5150 6450 5050
|
||||
$Sheet
|
||||
S 4550 2700 2250 2250
|
||||
U 5D77FDBE
|
||||
F0 "LogicBlock" 50
|
||||
F1 "logic_block.sch" 50
|
||||
F2 "fabric_b[3..0]" I R 6800 4850 50
|
||||
F3 "fabric_t[3..0]" I R 6800 2800 50
|
||||
F4 "fabric_l[3..0]" I L 4550 4550 50
|
||||
F5 "fabric_r[3..0]" I R 6800 4550 50
|
||||
F6 "rst_n" I L 4550 3100 50
|
||||
F7 "clk" I L 4550 3000 50
|
||||
F8 "isp_mosi" I L 4550 3400 50
|
||||
F9 "isp_sck" I L 4550 3300 50
|
||||
F10 "isp_miso" O R 6800 3400 50
|
||||
$EndSheet
|
||||
Wire Bus Line
|
||||
6800 4850 6900 4850
|
||||
Wire Bus Line
|
||||
6900 4850 6900 5050
|
||||
Wire Wire Line
|
||||
5450 5600 5450 3000
|
||||
Connection ~ 5450 3000
|
||||
Wire Wire Line
|
||||
5450 3000 7400 3000
|
||||
Wire Wire Line
|
||||
5550 5600 5550 3100
|
||||
Connection ~ 5550 3100
|
||||
Wire Wire Line
|
||||
5550 3100 7300 3100
|
||||
Wire Wire Line
|
||||
5650 5600 5650 3300
|
||||
Connection ~ 5650 3300
|
||||
Wire Bus Line
|
||||
3900 4550 4550 4550
|
||||
Wire Wire Line
|
||||
5750 4050 5750 5600
|
||||
Wire Wire Line
|
||||
3350 4050 5750 4050
|
||||
Text Notes 6400 5850 3 63 ~ 0
|
||||
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI3\nI2\nI1\nI0
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Female J4
|
||||
U 1 1 60090C3D
|
||||
P 5750 5800
|
||||
F 0 "J4" H 5700 6400 50 0000 C CNN
|
||||
F 1 "Bottom" V 5650 5050 50 0000 C CNN
|
||||
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 5750 5800 50 0001 C CNN
|
||||
F 3 "~" H 5750 5800 50 0001 C CNN
|
||||
1 5750 5800
|
||||
0 -1 1 0
|
||||
$EndComp
|
||||
Text Notes 6400 1800 1 63 ~ 0
|
||||
VCC\nGND\nCLK\nRST\nSCK\nMOSI_D\n\n\nI3\nI2\nI1\nI0
|
||||
$Comp
|
||||
L power:VCC #PWR01
|
||||
U 1 1 600A7963
|
||||
P 5150 2150
|
||||
F 0 "#PWR01" H 5150 2000 50 0001 C CNN
|
||||
F 1 "VCC" H 5250 2200 50 0000 C CNN
|
||||
F 2 "" H 5150 2150 50 0001 C CNN
|
||||
F 3 "" H 5150 2150 50 0001 C CNN
|
||||
1 5150 2150
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5250 2250 5150 2250
|
||||
Wire Wire Line
|
||||
5250 2050 5250 2250
|
||||
Text Label 6050 2500 1 50 ~ 0
|
||||
fabric_t3
|
||||
Text Label 6150 2500 1 50 ~ 0
|
||||
fabric_t2
|
||||
Text Label 6250 2500 1 50 ~ 0
|
||||
fabric_t1
|
||||
Text Label 6350 2500 1 50 ~ 0
|
||||
fabric_t0
|
||||
Wire Wire Line
|
||||
6350 2050 6350 2500
|
||||
Wire Wire Line
|
||||
6250 2050 6250 2500
|
||||
Wire Wire Line
|
||||
6150 2050 6150 2500
|
||||
Wire Wire Line
|
||||
6050 2050 6050 2500
|
||||
Entry Wire Line
|
||||
6250 2500 6350 2600
|
||||
Entry Wire Line
|
||||
6150 2500 6250 2600
|
||||
Entry Wire Line
|
||||
6050 2500 6150 2600
|
||||
Entry Wire Line
|
||||
6350 2500 6450 2600
|
||||
Wire Bus Line
|
||||
6900 2800 6800 2800
|
||||
Wire Bus Line
|
||||
6900 2600 6900 2800
|
||||
Text Label 6250 5050 0 50 ~ 0
|
||||
fabric_b[3..0]
|
||||
Text Label 6450 2600 0 50 ~ 0
|
||||
fabric_t[3..0]
|
||||
Wire Wire Line
|
||||
5450 2050 5450 3000
|
||||
Wire Wire Line
|
||||
5550 3100 5550 2050
|
||||
Wire Wire Line
|
||||
5650 3300 7200 3300
|
||||
Wire Wire Line
|
||||
5650 3300 5650 2050
|
||||
Wire Notes Line
|
||||
6400 3400 4950 3400
|
||||
Wire Notes Line
|
||||
6400 3400 6300 3350
|
||||
Wire Notes Line
|
||||
6400 3400 6300 3450
|
||||
Text Label 6900 4550 0 50 ~ 0
|
||||
fabric_r[3..0]
|
||||
Wire Wire Line
|
||||
5750 2050 5750 2500
|
||||
Wire Wire Line
|
||||
5750 2500 4300 2500
|
||||
Wire Wire Line
|
||||
4300 2500 4300 3400
|
||||
Connection ~ 4300 3400
|
||||
Wire Wire Line
|
||||
4300 3400 4550 3400
|
||||
Wire Notes Line
|
||||
8550 3850 8650 3850
|
||||
Wire Notes Line
|
||||
8550 3950 8600 3900
|
||||
Wire Notes Line
|
||||
8550 3950 8600 4000
|
||||
Wire Notes Line
|
||||
8650 3950 8550 3950
|
||||
Wire Notes Line
|
||||
8650 3850 8650 3950
|
||||
Wire Notes Line
|
||||
2850 3950 2600 3950
|
||||
Wire Notes Line
|
||||
2600 3950 2600 4050
|
||||
Wire Notes Line
|
||||
2600 4050 2700 4050
|
||||
Wire Notes Line
|
||||
2650 4000 2700 4050
|
||||
Wire Notes Line
|
||||
2700 4050 2650 4100
|
||||
Wire Notes Line
|
||||
2450 3850 2850 3850
|
||||
Wire Notes Line
|
||||
2850 3850 2800 3800
|
||||
Wire Notes Line
|
||||
2850 3850 2800 3900
|
||||
Wire Notes Line
|
||||
5750 6200 5750 6350
|
||||
Wire Notes Line
|
||||
5750 6350 5700 6300
|
||||
Wire Notes Line
|
||||
5750 6350 5800 6300
|
||||
Wire Notes Line
|
||||
5750 1300 5750 1450
|
||||
Wire Notes Line
|
||||
5750 1450 5700 1400
|
||||
Wire Notes Line
|
||||
5750 1450 5800 1400
|
||||
Text Notes 1900 3850 0 50 ~ 0
|
||||
PROGRAMMER
|
||||
Wire Notes Line
|
||||
2850 3750 2450 3750
|
||||
Wire Notes Line
|
||||
2850 3750 2800 3700
|
||||
Wire Notes Line
|
||||
2850 3750 2800 3800
|
||||
Wire Notes Line
|
||||
2450 3650 2450 3950
|
||||
Wire Notes Line
|
||||
2450 3950 1850 3950
|
||||
Wire Notes Line
|
||||
1850 3950 1850 3650
|
||||
Wire Notes Line
|
||||
1850 3650 2450 3650
|
||||
Wire Wire Line
|
||||
5850 5600 5850 2050
|
||||
Wire Wire Line
|
||||
5350 2250 5350 2050
|
||||
$Comp
|
||||
L power:GNDD #PWR02
|
||||
U 1 1 600A7959
|
||||
P 5350 2250
|
||||
F 0 "#PWR02" H 5350 2000 50 0001 C CNN
|
||||
F 1 "GNDD" H 5354 2095 50 0000 C CNN
|
||||
F 2 "" H 5350 2250 50 0001 C CNN
|
||||
F 3 "" H 5350 2250 50 0001 C CNN
|
||||
1 5350 2250
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5150 2250 5150 2150
|
||||
Wire Wire Line
|
||||
5200 5150 5200 5200
|
||||
NoConn ~ 5950 2050
|
||||
NoConn ~ 8000 4050
|
||||
NoConn ~ 5950 5600
|
||||
Wire Notes Line
|
||||
3150 1850 8200 1850
|
||||
Wire Notes Line
|
||||
8200 1850 8200 5800
|
||||
Wire Notes Line
|
||||
8200 5800 3150 5800
|
||||
Wire Notes Line
|
||||
3150 5800 3150 1850
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Male J1
|
||||
U 1 1 5CF30EFB
|
||||
P 5750 1850
|
||||
F 0 "J1" H 5850 2450 50 0000 R CNN
|
||||
F 1 "Top" V 5850 1200 50 0000 R CNN
|
||||
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 5750 1850 50 0001 C CNN
|
||||
F 3 "~" H 5750 1850 50 0001 C CNN
|
||||
1 5750 1850
|
||||
0 -1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Male J3
|
||||
U 1 1 5CF23FEF
|
||||
P 8200 3850
|
||||
F 0 "J3" H 8300 4450 50 0000 R CNN
|
||||
F 1 "Right" H 8400 3200 50 0000 R CNN
|
||||
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Horizontal" H 8200 3850 50 0001 C CNN
|
||||
F 3 "~" H 8200 3850 50 0001 C CNN
|
||||
1 8200 3850
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x12_Female J2
|
||||
U 1 1 5FE88CA2
|
||||
P 3150 3850
|
||||
F 0 "J2" H 3100 4450 50 0000 C CNN
|
||||
F 1 "Left" H 3050 3200 50 0000 C CNN
|
||||
F 2 "Connector_PinSocket_2.54mm:PinSocket_1x12_P2.54mm_Horizontal" H 3150 3850 50 0001 C CNN
|
||||
F 3 "~" H 3150 3850 50 0001 C CNN
|
||||
1 3150 3850
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:CP C1
|
||||
U 1 1 5CF70F0E
|
||||
P 3550 5150
|
||||
F 0 "C1" H 3668 5196 50 0000 L CNN
|
||||
F 1 "10u" H 3668 5105 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_1206_3216Metric" H 3588 5000 50 0001 C CNN
|
||||
F 3 "~" H 3550 5150 50 0001 C CNN
|
||||
1 3550 5150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:VCC #PWR07
|
||||
U 1 1 5CF715DB
|
||||
P 3550 4900
|
||||
F 0 "#PWR07" H 3550 4750 50 0001 C CNN
|
||||
F 1 "VCC" H 3567 5073 50 0000 C CNN
|
||||
F 2 "" H 3550 4900 50 0001 C CNN
|
||||
F 3 "" H 3550 4900 50 0001 C CNN
|
||||
1 3550 4900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3550 5000 3550 4900
|
||||
$Comp
|
||||
L Device:LED D?
|
||||
U 1 1 5CFB92E6
|
||||
P 4150 5200
|
||||
AR Path="/5D77FDBE/5D7AF013/5CFB92E6" Ref="D?" Part="1"
|
||||
AR Path="/5D77FDBE/5CFB92E6" Ref="D?" Part="1"
|
||||
AR Path="/5CFB92E6" Ref="D1" Part="1"
|
||||
F 0 "D1" V 4200 5100 50 0000 R CNN
|
||||
F 1 "PWR" V 4100 5100 50 0000 R CNN
|
||||
F 2 "LED_SMD:LED_0603_1608Metric" H 4150 5200 50 0001 C CNN
|
||||
F 3 "~" H 4150 5200 50 0001 C CNN
|
||||
1 4150 5200
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:R R?
|
||||
U 1 1 5CFB92EC
|
||||
P 3950 5000
|
||||
AR Path="/5D77FDBE/5D7AF013/5CFB92EC" Ref="R?" Part="1"
|
||||
AR Path="/5D77FDBE/5CFB92EC" Ref="R?" Part="1"
|
||||
AR Path="/5CFB92EC" Ref="R1" Part="1"
|
||||
F 0 "R1" H 4020 5046 50 0000 L CNN
|
||||
F 1 "470" H 4020 4955 50 0000 L CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 3880 5000 50 0001 C CNN
|
||||
F 3 "~" H 3950 5000 50 0001 C CNN
|
||||
1 3950 5000
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:VCC #PWR08
|
||||
U 1 1 5CFBED78
|
||||
P 3750 4900
|
||||
F 0 "#PWR08" H 3750 4750 50 0001 C CNN
|
||||
F 1 "VCC" H 3767 5073 50 0000 C CNN
|
||||
F 2 "" H 3750 4900 50 0001 C CNN
|
||||
F 3 "" H 3750 4900 50 0001 C CNN
|
||||
1 3750 4900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3800 5000 3750 5000
|
||||
Wire Wire Line
|
||||
3750 5000 3750 4900
|
||||
Wire Wire Line
|
||||
4100 5000 4150 5000
|
||||
Wire Wire Line
|
||||
4150 5000 4150 5050
|
||||
Wire Wire Line
|
||||
3550 5400 3550 5300
|
||||
$Comp
|
||||
L power:GNDD #PWR010
|
||||
U 1 1 5CF71B50
|
||||
P 3550 5400
|
||||
F 0 "#PWR010" H 3550 5150 50 0001 C CNN
|
||||
F 1 "GNDD" V 3554 5290 50 0000 R CNN
|
||||
F 2 "" H 3550 5400 50 0001 C CNN
|
||||
F 3 "" H 3550 5400 50 0001 C CNN
|
||||
1 3550 5400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4150 5350 4150 5400
|
||||
$Comp
|
||||
L power:GNDD #PWR011
|
||||
U 1 1 5CFBCC03
|
||||
P 4150 5400
|
||||
F 0 "#PWR011" H 4150 5150 50 0001 C CNN
|
||||
F 1 "GNDD" V 4154 5290 50 0000 R CNN
|
||||
F 2 "" H 4150 5400 50 0001 C CNN
|
||||
F 3 "" H 4150 5400 50 0001 C CNN
|
||||
1 4150 5400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
8000 4450 7550 4450
|
||||
Text Label 3450 4050 0 50 ~ 0
|
||||
mosi_d
|
||||
Text Label 3450 3950 0 50 ~ 0
|
||||
miso
|
||||
Wire Bus Line
|
||||
7450 4250 7450 4550
|
||||
Wire Bus Line
|
||||
3900 4250 3900 4550
|
||||
Wire Bus Line
|
||||
6150 2600 6900 2600
|
||||
Wire Bus Line
|
||||
6150 5050 6900 5050
|
||||
$EndSCHEMATC
|
|
@ -0,0 +1,5 @@
|
|||
*.user
|
||||
*~
|
||||
Makefile
|
||||
*.autosave
|
||||
build-*
|
|
@ -0,0 +1,8 @@
|
|||
cmake_minimum_required(VERSION 2.8)
|
||||
|
||||
project(kousaten)
|
||||
#set(CMAKE_BUILD_TYPE Release)
|
||||
set(CMAKE_C_FLAGS "-Wall")
|
||||
|
||||
aux_source_directory(./src SRC_LIST)
|
||||
add_executable(${PROJECT_NAME} ${SRC_LIST})
|
|
@ -0,0 +1,2 @@
|
|||
# TTL-FPGA Compiler *Kousaten*
|
||||
Tool to generate bitstreams for the TTL-FPGA after manual synthesis and PNR.
|
|
@ -0,0 +1,4 @@
|
|||
PLLLL]
|
||||
[LLLL]
|
||||
[LLLL]
|
||||
[LLLL
|
|
@ -0,0 +1 @@
|
|||
PL
|
|
@ -0,0 +1,9 @@
|
|||
#!/bin/bash
|
||||
|
||||
if [ $# -lt 2 ]; then
|
||||
echo "Usage: $0 </dev/ttyX> <progfile>"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
stty -F "$1" raw
|
||||
cat "$2" > "$1"
|
|
@ -0,0 +1,56 @@
|
|||
#include "fpga.h"
|
||||
#include "fpga_global.h"
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
int fpga_generate_bitstream(struct fpga_chain *chain,
|
||||
char *filename, int ascii)
|
||||
{
|
||||
int i;
|
||||
char *buf = NULL;
|
||||
FILE *bitstream = stdout;
|
||||
|
||||
if (strcmp(filename, "-")) {
|
||||
bitstream = fopen(filename, "wb");
|
||||
}
|
||||
if (!bitstream) {
|
||||
report(LL_ERROR,
|
||||
"Could not open output file '%s'.",
|
||||
filename);
|
||||
errno = EIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
report(LL_INFO, "Generating bitstream...");
|
||||
|
||||
for (i = chain->length - 1; i >= 0; --i) {
|
||||
report(LL_DEBUG,
|
||||
"Generating bitstream for cell %p (%c)...",
|
||||
chain->head[i], chain->head[i]->type->identifier);
|
||||
buf = chain->head[i]->type->isp_generate_bitstream(chain->head[i]);
|
||||
if (!buf) {
|
||||
report(LL_ERROR,
|
||||
"Error during bitstream generation for cell %p.",
|
||||
chain->head[i]);
|
||||
errno = ETYPE;
|
||||
goto fail;
|
||||
}
|
||||
for (int j = 0; j < chain->head[i]->type->isp_length; ++j) {
|
||||
if (ascii)
|
||||
fprintf(bitstream, "%02X ", buf[j] & 0xFF);
|
||||
else
|
||||
fputc(buf[j] & 0xFF, bitstream);
|
||||
}
|
||||
if (ascii)
|
||||
fprintf(bitstream, "\n");
|
||||
free(buf);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (bitstream && (strcmp(filename, "-")))
|
||||
fclose(bitstream);
|
||||
return 1;
|
||||
}
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef FPGA_H
|
||||
#define FPGA_H
|
||||
#include "fpga_cell.h"
|
||||
|
||||
int fpga_generate_bitstream(struct fpga_chain *chain,
|
||||
char *filename, int ascii);
|
||||
|
||||
#endif // FPGA_H
|
|
@ -0,0 +1,329 @@
|
|||
#include "fpga_cell.h"
|
||||
#include "fpga_global.h"
|
||||
#include "fpga_cell_lut34.h"
|
||||
#include "fpga_cell_none.h"
|
||||
#include "fpga_cell_wire.h"
|
||||
#include <stdlib.h>
|
||||
|
||||
static struct fpga_cell_type fpga_cell_list[] = {
|
||||
{
|
||||
.identifier = ' ',
|
||||
.cell_new = fpga_cell_none_new,
|
||||
.get_next_isp = fpga_cell_none_get_next_isp,
|
||||
.isp_length = 0,
|
||||
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
|
||||
},
|
||||
{
|
||||
.identifier = '[',
|
||||
.cell_new = fpga_cell_wire_new,
|
||||
.get_next_isp = fpga_cell_wire_get_next_isp,
|
||||
.isp_length = 0,
|
||||
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
|
||||
},
|
||||
{
|
||||
.identifier = ']',
|
||||
.cell_new = fpga_cell_wire_new,
|
||||
.get_next_isp = fpga_cell_wire_get_next_isp,
|
||||
.isp_length = 0,
|
||||
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
|
||||
},
|
||||
{
|
||||
.identifier = 'P',
|
||||
.cell_new = fpga_cell_wire_new,
|
||||
.get_next_isp = fpga_cell_wire_get_next_isp,
|
||||
.isp_length = 0,
|
||||
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
|
||||
},
|
||||
{
|
||||
.identifier = 'L',
|
||||
.cell_new = fpga_cell_lut34_new,
|
||||
.get_next_isp = fpga_cell_lut34_get_next_isp,
|
||||
.isp_length = 6,
|
||||
.isp_generate_bitstream = fpga_cell_lut34_isp_generate_bitstream
|
||||
},
|
||||
{
|
||||
.identifier = '\0',
|
||||
.cell_new = NULL,
|
||||
.get_next_isp = NULL,
|
||||
.isp_length = 0,
|
||||
.isp_generate_bitstream = fpga_cell_isp_generate_bitstream_dummy
|
||||
}
|
||||
};
|
||||
|
||||
void fpga_cell_init(struct fpga_cell *cell,
|
||||
struct fpga_cell_type *cell_type)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < FPGA_CELL_CONNECTION_COUNT; ++i) {
|
||||
cell->cell_connections[i] = NULL;
|
||||
}
|
||||
|
||||
cell->type = cell_type;
|
||||
//fpga_cell->get_next_isp = fpga_cell_get_next_isp_dummy;
|
||||
|
||||
report(LL_DEBUG,
|
||||
"Initialized cell of type %d at %p.",
|
||||
cell_type, cell);
|
||||
}
|
||||
|
||||
enum fpga_cell_position fpga_cell_connection_opposing(enum fpga_cell_position position)
|
||||
{
|
||||
switch (position) {
|
||||
case LEFT:
|
||||
return RIGHT;
|
||||
case RIGHT:
|
||||
return LEFT;
|
||||
case TOP:
|
||||
return BOTTOM;
|
||||
case BOTTOM:
|
||||
return TOP;
|
||||
default:
|
||||
report(LL_ERROR,
|
||||
"Internal error: Requested opposite of invalid position %d.",
|
||||
position);
|
||||
return LEFT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief fpga_cell_connect Connect <fpga_cell> to the <position> of <target_cell>
|
||||
* @param fpga_cell
|
||||
* @param target_cell
|
||||
* @param position
|
||||
* @return 0 on success, -1 on failure
|
||||
*/
|
||||
int fpga_cell_connect(struct fpga_cell *fpga_cell,
|
||||
struct fpga_cell *target_cell,
|
||||
enum fpga_cell_position position)
|
||||
{
|
||||
if (target_cell->cell_connections[position] ||
|
||||
fpga_cell->cell_connections[fpga_cell_connection_opposing(position)]) {
|
||||
report(LL_WARNING,
|
||||
"Tried to connect cell %p to pos %d of %p, even though a connection already exists for a least one of them.",
|
||||
fpga_cell, target_cell, position);
|
||||
errno = -ECONN;
|
||||
return -1;
|
||||
}
|
||||
|
||||
target_cell->cell_connections[position] = fpga_cell;
|
||||
fpga_cell->cell_connections[fpga_cell_connection_opposing(position)] = target_cell;
|
||||
|
||||
report(LL_DEBUG,
|
||||
"Connected cell %p to port %d of %p.",
|
||||
fpga_cell, position, target_cell);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief fpga_cell_get_far Get cell on the far <position> of <cell>
|
||||
* @param cell
|
||||
* @param position
|
||||
* @return
|
||||
*/
|
||||
struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell,
|
||||
enum fpga_cell_position position)
|
||||
{
|
||||
struct fpga_cell *next = cell;
|
||||
|
||||
while (next->cell_connections[position]) {
|
||||
next = next->cell_connections[position];
|
||||
}
|
||||
|
||||
return next;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief fpga_cell_get_next_isp Get the next cell in the ISP chain
|
||||
* @param fpga_cell the current cell in the ISP chain
|
||||
* @param isp_channel the current channel. This will be updated when calling this function!
|
||||
* @return the next ISP cell
|
||||
*/
|
||||
struct fpga_cell *fpga_cell_get_next_isp_dummy(struct fpga_cell *cell,
|
||||
enum fpga_isp_channel *isp_channel)
|
||||
{
|
||||
report(LL_CRITICAL,
|
||||
"Internal error. Cell type %c does not implement get_next_isp!",
|
||||
cell->type->identifier);
|
||||
*isp_channel = FPGA_ISP_CHANNEL_ERROR;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief isp_generate_bitstream_dummy
|
||||
* @param cell
|
||||
* @param buf
|
||||
* @return
|
||||
*/
|
||||
char *fpga_cell_isp_generate_bitstream_dummy(struct fpga_cell *cell)
|
||||
{
|
||||
report(LL_CRITICAL,
|
||||
"Internal error. Cell type %c does not implement isp_generate_bitstream!",
|
||||
cell->type->identifier);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief fpga_cell_new Create a new instance of type <identifier>
|
||||
* @param identifier
|
||||
* @return
|
||||
*/
|
||||
struct fpga_cell *fpga_cell_new(char identifier)
|
||||
{
|
||||
struct fpga_cell_type *cell_type = fpga_cell_list;
|
||||
struct fpga_cell *cell = NULL;
|
||||
|
||||
while (cell_type->identifier) {
|
||||
if (identifier == cell_type->identifier) {
|
||||
cell = cell_type->cell_new();
|
||||
if (!cell) {
|
||||
report(LL_CRITICAL,
|
||||
"Out of memory when creating cell.");
|
||||
return NULL;
|
||||
}
|
||||
cell->type = cell_type;
|
||||
report(LL_DEBUG,
|
||||
"Created cell %p of type %c.",
|
||||
cell, identifier);
|
||||
return cell;
|
||||
}
|
||||
cell_type++;
|
||||
}
|
||||
|
||||
report(LL_ERROR,
|
||||
"Invalid cell type %c found in FDEF.",
|
||||
identifier);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief fpga_isp_chain_new
|
||||
* @param entry
|
||||
* @return
|
||||
*/
|
||||
struct fpga_chain *fpga_isp_chain_new(struct fpga_cell *entry)
|
||||
{
|
||||
struct fpga_cell *current_cell = entry;
|
||||
enum fpga_isp_channel current_channel = FPGA_ISP_CHANNEL_NORMAL;
|
||||
struct fpga_chain *chain;
|
||||
|
||||
report(LL_INFO,
|
||||
"Generating ISP chain...");
|
||||
|
||||
if (entry->type->identifier != 'P') {
|
||||
report(LL_CRITICAL,
|
||||
"Entry cell must be of type P, was '%c'",
|
||||
entry->type->identifier);
|
||||
errno = EINVAL;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
chain = calloc(sizeof (struct fpga_chain), 1);
|
||||
if (!chain) {
|
||||
report (LL_CRITICAL,
|
||||
"Out of memory during ISP chain generation.");
|
||||
errno = ENOMEM;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
while (current_cell) {
|
||||
if (current_channel == FPGA_ISP_CHANNEL_NORMAL &&
|
||||
current_cell->type->isp_length > 0) {
|
||||
report(LL_DEBUG,
|
||||
"Adding %p (%c) to ISP chain.",
|
||||
current_cell, current_cell->type->identifier);
|
||||
|
||||
if (!chain->head) {
|
||||
chain->head = malloc(sizeof(chain->head));
|
||||
*(chain->head) = current_cell;
|
||||
chain->length = 1;
|
||||
} else {
|
||||
chain->length++;
|
||||
chain->head = realloc(chain->head,
|
||||
sizeof(chain->head) * chain->length);
|
||||
*(chain->head + chain->length - 1) = current_cell;
|
||||
}
|
||||
|
||||
} else {
|
||||
report(LL_DEBUG,
|
||||
"Using %p (%c) for ISP routing.",
|
||||
current_cell, current_cell->type->identifier);
|
||||
}
|
||||
|
||||
current_cell = current_cell->type->get_next_isp(current_cell,
|
||||
¤t_channel);
|
||||
if (current_channel == FPGA_ISP_CHANNEL_ERROR) {
|
||||
/* TODO: Clean up memory */
|
||||
errno = ETYPE;
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
report(LL_INFO,
|
||||
"Added %d cells to ISP chain.",
|
||||
chain->length);
|
||||
|
||||
for (int i = 0; i < chain->length; ++i) {
|
||||
report(LL_DEBUG,
|
||||
" %4d = %p",
|
||||
i, chain->head[i]);
|
||||
}
|
||||
|
||||
report(LL_INFO,
|
||||
"ISP chain generation finished.");
|
||||
|
||||
return chain;
|
||||
}
|
||||
|
||||
int fpga_cell_bitstream_set_bit(char *buffer, char *sbuffer,
|
||||
int bit, int value) {
|
||||
int byteno;
|
||||
int bitno;
|
||||
|
||||
bit = 47 - bit;
|
||||
|
||||
bitno = 7 - (bit % 8);
|
||||
byteno = bit / 8;
|
||||
|
||||
value = !!value; /* Make sure it's a proper boolean value */
|
||||
|
||||
if ((sbuffer[byteno] & (1 << bitno))) { /* Already set */
|
||||
return value == !((buffer[byteno] & (1 << bitno)));
|
||||
} else {
|
||||
sbuffer[byteno] |= (1 << bitno);
|
||||
if (value)
|
||||
buffer[byteno] |= (1 << bitno);
|
||||
else
|
||||
buffer[byteno] &= ~(1 << bitno);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fpga_cell_bitstream_set_bits(char *buffer, char *sbuffer,
|
||||
int value, int nbits, int *mapping)
|
||||
{
|
||||
int i;
|
||||
int ret = 0;
|
||||
|
||||
for (i = 0; i < nbits; ++i) {
|
||||
ret = ret || fpga_cell_bitstream_set_bit(buffer, sbuffer,
|
||||
mapping[i], value & (1 << i));
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fpga_cell_bitstream_is_set(char *buffer, int bit)
|
||||
{
|
||||
int byteno;
|
||||
int bitno;
|
||||
|
||||
bit = 47 - bit;
|
||||
|
||||
bitno = 7 - (bit % 8);
|
||||
byteno = bit / 8;
|
||||
|
||||
return !!(buffer[byteno] & (1 << bitno));
|
||||
}
|
|
@ -0,0 +1,67 @@
|
|||
#ifndef FPGA_CELL_H
|
||||
#define FPGA_CELL_H
|
||||
#include <stddef.h>
|
||||
|
||||
enum fpga_cell_position {
|
||||
LEFT = 0,
|
||||
TOP,
|
||||
RIGHT,
|
||||
BOTTOM,
|
||||
FPGA_CELL_CONNECTION_COUNT
|
||||
};
|
||||
|
||||
enum fpga_isp_channel {
|
||||
FPGA_ISP_CHANNEL_NORMAL = 0,
|
||||
FPGA_ISP_CHANNEL_BACK,
|
||||
FPGA_ISP_CHANNEL_LFDN,
|
||||
FPGA_ISP_CHANNEL_DNUP,
|
||||
FPGA_ISP_CHANNEL_ERROR
|
||||
};
|
||||
|
||||
struct fpga_cell_type
|
||||
{
|
||||
char identifier;
|
||||
|
||||
struct fpga_cell *(*cell_new)();
|
||||
struct fpga_cell *(*get_next_isp)(struct fpga_cell *cell,
|
||||
enum fpga_isp_channel *isp_channel);
|
||||
unsigned long isp_length;
|
||||
char *(*isp_generate_bitstream)(struct fpga_cell *cell);
|
||||
};
|
||||
|
||||
/* FPGA Logic cell base parameters */
|
||||
struct fpga_cell
|
||||
{
|
||||
struct fpga_cell_type *type;
|
||||
|
||||
struct fpga_cell *cell_connections[FPGA_CELL_CONNECTION_COUNT];
|
||||
|
||||
/* Cell-specific data will be appended depending on the cell type. */
|
||||
};
|
||||
|
||||
struct fpga_chain {
|
||||
struct fpga_cell **head;
|
||||
int length;
|
||||
};
|
||||
|
||||
void fpga_cell_init(struct fpga_cell *cell,
|
||||
struct fpga_cell_type *cell_type);
|
||||
int fpga_cell_connect(struct fpga_cell *fpga_cell,
|
||||
struct fpga_cell *target_cell,
|
||||
enum fpga_cell_position position);
|
||||
struct fpga_cell *fpga_cell_get_far(struct fpga_cell *cell,
|
||||
enum fpga_cell_position position);
|
||||
struct fpga_cell *fpga_cell_get_next_isp_dummy(struct fpga_cell *fpga_cell,
|
||||
enum fpga_isp_channel *isp_channel);
|
||||
char *fpga_cell_isp_generate_bitstream_dummy(struct fpga_cell *cell);
|
||||
struct fpga_cell *fpga_cell_new(char identifier);
|
||||
#define FPGA_TO_CELL(a) ((struct fpga_cell*) a)
|
||||
|
||||
struct fpga_chain *fpga_isp_chain_new(struct fpga_cell *entry);
|
||||
int fpga_cell_bitstream_set_bit(char *buffer, char *sbuffer,
|
||||
int bit, int value);
|
||||
int fpga_cell_bitstream_set_bits(char *buffer, char *sbuffer,
|
||||
int value, int nbits, int *mapping);
|
||||
int fpga_cell_bitstream_is_set(char *buffer, int bit);
|
||||
|
||||
#endif // FPGA_CELL_H
|
|
@ -0,0 +1,300 @@
|
|||
#include "fpga_cell_lut34.h"
|
||||
#include "fpga_global.h"
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#define LUTD_POSITION 16 /* First bit of LUTD cfg bits */
|
||||
#define LUTD_BIT_COUNT 16 /* To be applied for any cfg no > 15 */
|
||||
|
||||
static int need_fix = 1;
|
||||
|
||||
/* LUT Definitions (correct offset, no fix must be applied) */
|
||||
static int LUT4_BITMAP[16] = {
|
||||
24, 25, 26, 27, 28, 29, 30, 31,
|
||||
16, 17, 18, 19, 20, 21, 22, 23
|
||||
};
|
||||
static int LUT3_BITMAP[2][8] = {
|
||||
{24, 25, 26, 27, 28, 29, 30, 31},
|
||||
{16, 17, 18, 19, 20, 21, 22, 23}
|
||||
};
|
||||
|
||||
/* LUT Config Definitions */
|
||||
static int BIT_LUT_SYNC_N = 20;
|
||||
static int BIT_LUT_SPLIT_N = 21;
|
||||
|
||||
/* LUT IN MUX Definitions */
|
||||
static char LUT_IN_MUX[4][8] = {
|
||||
{LUT_NET_F2, LUT_NET_L0, LUT_NET_L3, LUT_NET_L2, LUT_NET_L1, LUT_NET_F1, LUT_NET_F0, LUT_NET_T0},
|
||||
{LUT_NET_F0, LUT_NET_F1, LUT_NET_L1, LUT_NET_L2, LUT_NET_L3, LUT_NET_L0, LUT_NET_F2, LUT_NET_T1},
|
||||
{LUT_NET_F3, LUT_NET_L0, LUT_NET_L3, LUT_NET_L2, LUT_NET_L1, LUT_NET_F1, LUT_NET_F0, LUT_NET_T2},
|
||||
{LUT_NET_F0, LUT_NET_F1, LUT_NET_L1, LUT_NET_L2, LUT_NET_L3, LUT_NET_L0, LUT_NET_F3, LUT_NET_T3}
|
||||
};
|
||||
static int LUT_IN_BITMAP[4][3] = {
|
||||
{12, 11, 19},
|
||||
{ 8, 9, 10},
|
||||
{15, 14, 13},
|
||||
{16, 17, 18}
|
||||
};
|
||||
|
||||
/* LUT OUT MUX Definitions */
|
||||
static int LUT_OUT_MUX[4][4] = {
|
||||
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
|
||||
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_A, LUT_OUT_A},
|
||||
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
|
||||
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
|
||||
};
|
||||
static int LUT_OUT_BITMAP[2][2] = {
|
||||
{27, 23},
|
||||
{25, 30}
|
||||
};
|
||||
static int LUT_OUT_EN_N_BITMAP[4] = {
|
||||
22, 26, 31, 24
|
||||
};
|
||||
|
||||
/* Routing Definitions */
|
||||
static int ROUTE_BITMAP[8] = {
|
||||
3, 6, 4, 0, /* Left */
|
||||
5, 1, 2, 7, /* Top */
|
||||
};
|
||||
|
||||
/* LED Definitions */
|
||||
static int BIT_LED_LUT_IN = 28;
|
||||
static int BIT_LED_LUT_OUT_N = 29; /* Low-active */
|
||||
|
||||
static inline int fpga_cell_lut34_is_driven(char drive_sel)
|
||||
{
|
||||
return (drive_sel != LUT_OUT_DC && drive_sel != LUT_OUT_Z);
|
||||
}
|
||||
|
||||
static int fpga_cell_lut34_lut_get_mux(int lut, char port)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (port == LUT_NET_DC)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < 8; ++i) {
|
||||
if (LUT_IN_MUX[lut][i] == port)
|
||||
return i;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports)
|
||||
{
|
||||
int i;
|
||||
int lut;
|
||||
|
||||
if (lut_group < 0 || lut_group > 2) {
|
||||
report(LL_ERROR,
|
||||
"Invalid LUT group requested.");
|
||||
return -1;
|
||||
}
|
||||
|
||||
lut = lut_group * 2;
|
||||
ports = ports + lut;
|
||||
|
||||
for (i = 0; i < 4; ++i) {
|
||||
if (!fpga_cell_lut34_is_driven(ports[0]) ||
|
||||
ports[0] == LUT_OUT_MUX[lut][i]) {
|
||||
if (!fpga_cell_lut34_is_driven(ports[1]) ||
|
||||
ports[1] == LUT_OUT_MUX[lut + 1][i])
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
struct fpga_cell *fpga_cell_lut34_new()
|
||||
{
|
||||
struct fpga_cell_lut34 *fpga_cell_lut_34;
|
||||
|
||||
fpga_cell_lut_34 = malloc(sizeof(struct fpga_cell_lut34));
|
||||
|
||||
fpga_cell_lut_34->LUT3[0] = -1;
|
||||
fpga_cell_lut_34->LUT3[1] = -1;
|
||||
fpga_cell_lut_34->LUT4 = -1;
|
||||
|
||||
return FPGA_TO_CELL(fpga_cell_lut_34);
|
||||
}
|
||||
|
||||
struct fpga_cell *fpga_cell_lut34_get_next_isp(struct fpga_cell *cell,
|
||||
enum fpga_isp_channel *isp_channel)
|
||||
{
|
||||
switch (*isp_channel) {
|
||||
case FPGA_ISP_CHANNEL_LFDN:
|
||||
*isp_channel = FPGA_ISP_CHANNEL_NORMAL;
|
||||
return cell->cell_connections[BOTTOM];
|
||||
case FPGA_ISP_CHANNEL_NORMAL:
|
||||
return cell->cell_connections[RIGHT];
|
||||
case FPGA_ISP_CHANNEL_BACK:
|
||||
return cell->cell_connections[LEFT];
|
||||
default:
|
||||
report(LL_ERROR,
|
||||
"Unhandled ISP channel %d for LUT34.",
|
||||
*isp_channel);
|
||||
}
|
||||
return NULL;
|
||||
|
||||
}
|
||||
|
||||
static void fix_bitfields(int *bitmap, int count)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count; ++i) {
|
||||
if (bitmap[i] >= LUTD_POSITION) {
|
||||
bitmap[i] += LUTD_BIT_COUNT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define BS_SET_BIT(bitno, value, errmsg, ...)\
|
||||
{if (fpga_cell_bitstream_set_bit(buf, sbuf, bitno, value)) {\
|
||||
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
|
||||
errno = ERECONF;\
|
||||
goto fail;\
|
||||
}} (void)0
|
||||
#define BS_SET_BITS(value, nbits, mapping, errmsg, ...) \
|
||||
{if (fpga_cell_bitstream_set_bits(buf, sbuf, value, nbits, mapping)) {\
|
||||
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
|
||||
errno = ERECONF;\
|
||||
goto fail;\
|
||||
}} (void)0
|
||||
|
||||
char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
|
||||
{
|
||||
struct fpga_cell_lut34 *lut34 = (struct fpga_cell_lut34 *) cell;
|
||||
char *buf = NULL;
|
||||
char *sbuf = NULL;
|
||||
int i;
|
||||
int temp;
|
||||
|
||||
buf = calloc(cell->type->isp_length, sizeof(char));
|
||||
sbuf = calloc(cell->type->isp_length, sizeof(char));
|
||||
|
||||
if (!buf || !sbuf) {
|
||||
report(LL_CRITICAL,
|
||||
"Out of memory during bitstream generation.");
|
||||
errno = ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Reposition cfg bits after LUTD cfg, cheap workaround to use the same
|
||||
cfg names as the schematic does. */
|
||||
if (need_fix) {
|
||||
need_fix = 0;
|
||||
for (i = 0; i < 4; ++i) {
|
||||
fix_bitfields(LUT_IN_BITMAP[i], 3);
|
||||
}
|
||||
for (i = 0; i < 2; ++i) {
|
||||
fix_bitfields(LUT_OUT_BITMAP[i], 2);
|
||||
}
|
||||
fix_bitfields(LUT_OUT_EN_N_BITMAP, 4);
|
||||
fix_bitfields(ROUTE_BITMAP, 8);
|
||||
fix_bitfields(&BIT_LED_LUT_IN, 1);
|
||||
fix_bitfields(&BIT_LED_LUT_OUT_N, 1);
|
||||
fix_bitfields(&BIT_LUT_SYNC_N, 1);
|
||||
fix_bitfields(&BIT_LUT_SPLIT_N, 1);
|
||||
}
|
||||
|
||||
|
||||
/* LEDs */
|
||||
BS_SET_BIT(BIT_LED_LUT_IN, 1,
|
||||
"Couldn't set LUT in LED to %d.", 1);
|
||||
BS_SET_BIT(BIT_LED_LUT_OUT_N, 0,
|
||||
"Couldn't set LUT out LED to %d.", 0);
|
||||
|
||||
/* LUT input sel */
|
||||
for (i = 0; i < 4; ++i) {
|
||||
temp = fpga_cell_lut34_lut_get_mux(i, lut34->lut_in_sel[i]);
|
||||
|
||||
if (temp < 0) {
|
||||
report(LL_ERROR,
|
||||
"Invalid input mux '%c' selected for mux %d on cell %p.",
|
||||
lut34->lut_in_sel[i], i, cell);
|
||||
errno = EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
BS_SET_BITS(temp, 3, LUT_IN_BITMAP[i], "Couldn't set LUT input sel for input %d.", i);
|
||||
}
|
||||
|
||||
/* LUT output sel + enable */
|
||||
for (i = 0; i < 2; ++i) {
|
||||
temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel);
|
||||
|
||||
if (temp < 0) {
|
||||
report(LL_ERROR,
|
||||
"Invalid output mux sel '%c' selected for net %d on cell %p.",
|
||||
lut34->drive_sel[i], i, cell);
|
||||
errno = EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
BS_SET_BITS(temp, 2, LUT_OUT_BITMAP[i],
|
||||
"Couldn't set LUT output sel %d for output %d.", temp, i);
|
||||
|
||||
}
|
||||
for (i = 0; i < 4; ++i) {
|
||||
temp = fpga_cell_lut34_is_driven(lut34->drive_sel[i]);
|
||||
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
|
||||
"Couldn't %s output for output %d.",
|
||||
(!temp ? "enable" : "disabled"), i);
|
||||
}
|
||||
|
||||
/* Routing */
|
||||
for (i = 0; i < 8; ++i) {
|
||||
BS_SET_BITS(lut34->route_en, 8, ROUTE_BITMAP,
|
||||
"Couldn't set routing bitmap to 0x%X for cell %p.",
|
||||
lut34->route_en, cell);
|
||||
}
|
||||
|
||||
/* LUTD */
|
||||
if (lut34->LUT4 > -1) {
|
||||
BS_SET_BITS(lut34->LUT4, 16, LUT4_BITMAP,
|
||||
"Error setting LUT4 data.");
|
||||
BS_SET_BIT(BIT_LUT_SPLIT_N, 1, "Couldn't set LUT4 mode.");
|
||||
}
|
||||
for (i = 0; i < 2; ++i) {
|
||||
if (lut34->LUT3[i] > -1) {
|
||||
BS_SET_BITS(lut34->LUT3[i], 8, LUT3_BITMAP[i],
|
||||
"Error setting LUT3[%d] data. Did you configure a LUT4 before?",
|
||||
i);
|
||||
BS_SET_BIT(BIT_LUT_SPLIT_N, 0, "Couldn't set LUT3-2 mode. Did you configure a LUT4 before?");
|
||||
}
|
||||
}
|
||||
BS_SET_BIT(BIT_LUT_SYNC_N, !lut34->sync, "Couldn't %s synchronous mode.",
|
||||
(lut34->sync ? "enabling" : "disabling"));
|
||||
|
||||
/* Basic check whether each bit has been configured */
|
||||
for (i = 0; i < cell->type->isp_length; ++i) {
|
||||
if ((sbuf[i] & 0xFF) != 255) {
|
||||
report(LL_WARNING,
|
||||
"Incomplete configuration for cell %p (byte %d: 0x%X).",
|
||||
cell, i, sbuf[i] & 0xFF);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
report(LL_DEBUG, "Bitstream result for %p:", cell);
|
||||
for (i = 0; i < 48; ++i) {
|
||||
report(LL_DEBUG,
|
||||
" %d: %d%s",
|
||||
i,
|
||||
fpga_cell_bitstream_is_set(buf, i),
|
||||
(fpga_cell_bitstream_is_set(sbuf, i) ? "" : " (Z)"));
|
||||
}
|
||||
|
||||
free(sbuf);
|
||||
|
||||
return buf;
|
||||
|
||||
fail:
|
||||
if (buf)
|
||||
free(buf);
|
||||
if (sbuf)
|
||||
free(sbuf);
|
||||
return NULL;
|
||||
}
|
|
@ -0,0 +1,61 @@
|
|||
#ifndef FPGA_CELL_LUT34_H
|
||||
#define FPGA_CELL_LUT34_H
|
||||
|
||||
#include "fpga_cell.h"
|
||||
|
||||
enum LUT_NET_NAMES {
|
||||
LUT_NET_DC = '\0', /* Dont' care */
|
||||
LUT_NET_T0 = '0',
|
||||
LUT_NET_T1 = '1',
|
||||
LUT_NET_T2 = '2',
|
||||
LUT_NET_T3 = '3',
|
||||
LUT_NET_L0 = 'A',
|
||||
LUT_NET_L1 = 'B',
|
||||
LUT_NET_L2 = 'C',
|
||||
LUT_NET_L3 = 'D',
|
||||
LUT_NET_F0 = 'W',
|
||||
LUT_NET_F1 = 'X',
|
||||
LUT_NET_F2 = 'Y',
|
||||
LUT_NET_F3 = 'Z'
|
||||
};
|
||||
|
||||
enum LUT_OUT_NAMES {
|
||||
LUT_OUT_DC = '\0', /* Don't care, treated like Z */
|
||||
LUT_OUT_Z = 'Z',
|
||||
LUT_OUT_C = 'C',
|
||||
LUT_OUT_A = 'A',
|
||||
LUT_OUT_B = 'B',
|
||||
LUT_OUT_B_ASYNC = 'b'
|
||||
};
|
||||
|
||||
enum ROUTE_NAMES {
|
||||
ROUTE_L0 = 0,
|
||||
ROUTE_L1,
|
||||
ROUTE_L2,
|
||||
ROUTE_L3,
|
||||
ROUTE_T0,
|
||||
ROUTE_T1,
|
||||
ROUTE_T2,
|
||||
ROUTE_T3
|
||||
};
|
||||
|
||||
struct fpga_cell_lut34 {
|
||||
struct fpga_cell base_cell;
|
||||
|
||||
int led_lut_in_enable;
|
||||
int led_lut_out_enable;
|
||||
|
||||
char lut_in_sel[4]; /* Input select */
|
||||
char drive_sel[4]; /* Which signal to drive onto each fabric line */
|
||||
int sync; /* Register output on rising edge of clk */
|
||||
int route_en; /* Bitfield, Enable routing between {left, top} and main fabric */
|
||||
|
||||
int LUT4; /* Look-up table for LUT-4 configuration */
|
||||
int LUT3[2]; /* Look-up tables for LUT-3 configuration */
|
||||
};
|
||||
|
||||
struct fpga_cell *fpga_cell_lut34_new();
|
||||
struct fpga_cell *fpga_cell_lut34_get_next_isp(struct fpga_cell *cell,
|
||||
enum fpga_isp_channel *isp_channel);
|
||||
char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell);
|
||||
#endif // FPGA_CELL_LUT34_H
|
|
@ -0,0 +1,20 @@
|
|||
#include "fpga_cell_none.h"
|
||||
#include <stdlib.h>
|
||||
#include "fpga_global.h"
|
||||
|
||||
struct fpga_cell *fpga_cell_none_new()
|
||||
{
|
||||
struct fpga_cell_none *fpga_cell_none;
|
||||
|
||||
fpga_cell_none = malloc(sizeof(struct fpga_cell_none));
|
||||
|
||||
return FPGA_TO_CELL(fpga_cell_none);
|
||||
}
|
||||
|
||||
struct fpga_cell *fpga_cell_none_get_next_isp(struct fpga_cell *fpga_cell,
|
||||
enum fpga_isp_channel *isp_channel)
|
||||
{
|
||||
report(LL_WARNING,
|
||||
"ISP signal ran into empty cell. Terminating chain.");
|
||||
return NULL;
|
||||
}
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef FPGA_CELL_NONE_H
|
||||
#define FPGA_CELL_NONE_H
|
||||
|
||||
#include "fpga_cell.h"
|
||||
|
||||
struct fpga_cell_none {
|
||||
struct fpga_cell base_cell;
|
||||
};
|
||||
|
||||
struct fpga_cell *fpga_cell_none_new();
|
||||
struct fpga_cell *fpga_cell_none_get_next_isp(struct fpga_cell *fpga_cell,
|
||||
enum fpga_isp_channel *isp_channel);
|
||||
|
||||
#endif // FPGA_CELL_NONE_H
|
|
@ -0,0 +1,48 @@
|
|||
#include "fpga_cell_wire.h"
|
||||
#include <stdlib.h>
|
||||
#include "fpga_global.h"
|
||||
|
||||
struct fpga_cell *fpga_cell_wire_new()
|
||||
{
|
||||
struct fpga_cell_wire *fpga_cell_wire;
|
||||
|
||||
fpga_cell_wire = malloc(sizeof(struct fpga_cell_wire));
|
||||
|
||||
return FPGA_TO_CELL(fpga_cell_wire);
|
||||
}
|
||||
|
||||
struct fpga_cell *fpga_cell_wire_get_next_isp(struct fpga_cell *cell,
|
||||
enum fpga_isp_channel *isp_channel)
|
||||
{
|
||||
switch (*isp_channel) {
|
||||
case FPGA_ISP_CHANNEL_NORMAL:
|
||||
switch (cell->type->identifier) {
|
||||
case 'P':
|
||||
return cell->cell_connections[RIGHT];
|
||||
case ']':
|
||||
*isp_channel = FPGA_ISP_CHANNEL_BACK;
|
||||
return cell->cell_connections[LEFT];
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
|
||||
case FPGA_ISP_CHANNEL_BACK:
|
||||
switch (cell->type->identifier) {
|
||||
case 'P':
|
||||
case '[':
|
||||
*isp_channel = FPGA_ISP_CHANNEL_LFDN;
|
||||
return cell->cell_connections[RIGHT];
|
||||
}
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
|
||||
fail:
|
||||
report(LL_ERROR,
|
||||
"Entered wiring cell %c on invalid ISP channel %d.",
|
||||
cell->type->identifier, *isp_channel);
|
||||
*isp_channel = FPGA_ISP_CHANNEL_ERROR;
|
||||
return NULL;
|
||||
|
||||
return NULL;
|
||||
}
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef FPGA_CELL_WIRE_H
|
||||
#define FPGA_CELL_WIRE_H
|
||||
|
||||
#include "fpga_cell.h"
|
||||
|
||||
struct fpga_cell_wire {
|
||||
struct fpga_cell base_cell;
|
||||
};
|
||||
|
||||
struct fpga_cell *fpga_cell_wire_new();
|
||||
struct fpga_cell *fpga_cell_wire_get_next_isp(struct fpga_cell *cell,
|
||||
enum fpga_isp_channel *isp_channel);
|
||||
|
||||
#endif // FPGA_CELL_WIRE_H
|
|
@ -0,0 +1,60 @@
|
|||
#include "fpga_fdef_loader.h"
|
||||
#include <stdio.h>
|
||||
|
||||
struct fpga_cell *fpga_fdef_loader_load(char *filename)
|
||||
{
|
||||
FILE *fdef;
|
||||
int c;
|
||||
int line = 1;
|
||||
int col = 1;
|
||||
|
||||
struct fpga_cell *cell_left = NULL;
|
||||
struct fpga_cell *cell_top = NULL;
|
||||
struct fpga_cell *cell = NULL;
|
||||
|
||||
report(LL_INFO, "Loading FDEF from %s...", filename);
|
||||
|
||||
fdef = fopen(filename, "r");
|
||||
|
||||
if (!fdef)
|
||||
return NULL;
|
||||
|
||||
while ((c = fgetc(fdef)) != EOF) {
|
||||
switch (c) {
|
||||
case '\n':
|
||||
col = 0;
|
||||
line++;
|
||||
break;
|
||||
|
||||
default:
|
||||
cell = fpga_cell_new((char) c);
|
||||
if (!cell) {
|
||||
/* TODO: clean up existing cells */
|
||||
return NULL;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (c == '\n') {
|
||||
cell_left = NULL;
|
||||
cell_top = fpga_cell_get_far(cell, LEFT);
|
||||
report(LL_DEBUG, "");
|
||||
|
||||
} else {
|
||||
if (cell_left)
|
||||
fpga_cell_connect(cell, cell_left, RIGHT);
|
||||
if (cell_top)
|
||||
fpga_cell_connect(cell, cell_top, BOTTOM);
|
||||
|
||||
cell_left = cell;
|
||||
if (cell_top)
|
||||
cell_top = cell_top->cell_connections[RIGHT];
|
||||
}
|
||||
|
||||
col++;
|
||||
}
|
||||
|
||||
fclose(fdef);
|
||||
|
||||
return fpga_cell_get_far(fpga_cell_get_far(cell, LEFT), TOP);
|
||||
}
|
|
@ -0,0 +1,11 @@
|
|||
#ifndef FPGA_FDEF_LOADER_H
|
||||
#define FPGA_FDEF_LOADER_H
|
||||
|
||||
#include "fpga_global.h"
|
||||
#include "fpga_cell.h"
|
||||
#include "fpga_cell_lut34.h"
|
||||
#include "fpga_cell_none.h"
|
||||
|
||||
struct fpga_cell *fpga_fdef_loader_load(char *filename);
|
||||
|
||||
#endif // FPGA_FDEF_LOADER_H
|
|
@ -0,0 +1,38 @@
|
|||
#include "fpga_global.h"
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
|
||||
static int current_log_level = 100;
|
||||
|
||||
static const char *ll_string[] = {
|
||||
"\x1B[31m\x1B[1m[X] ",
|
||||
"\x1B[31m[E] ",
|
||||
"\x1B[33m[W] ",
|
||||
"\x1B[32m[I] ",
|
||||
"\x1B[34m[D] ",
|
||||
"[?] "
|
||||
};
|
||||
|
||||
enum log_level report(enum log_level log_level, const char *format, ...)
|
||||
{
|
||||
va_list vargs;
|
||||
|
||||
if (log_level > LL_COUNT)
|
||||
log_level = LL_COUNT;
|
||||
|
||||
if (log_level <= current_log_level) {
|
||||
va_start(vargs, format);
|
||||
fprintf(stderr, "%s", ll_string[log_level]);
|
||||
vfprintf(stderr, format, vargs);
|
||||
fprintf(stderr, "\x1B[0m\n");
|
||||
va_end(vargs);
|
||||
}
|
||||
|
||||
return log_level;
|
||||
}
|
||||
|
||||
void set_log_level(enum log_level log_level)
|
||||
{
|
||||
current_log_level = log_level;
|
||||
}
|
|
@ -0,0 +1,20 @@
|
|||
#ifndef FPGA_GLOBAL_H
|
||||
#define FPGA_GLOBAL_H
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
enum log_level {LL_CRITICAL = 0,
|
||||
LL_ERROR,
|
||||
LL_WARNING,
|
||||
LL_INFO,
|
||||
LL_DEBUG,
|
||||
LL_COUNT};
|
||||
enum log_level report(enum log_level log_level, const char *format, ...);
|
||||
void set_log_level(enum log_level log_level);
|
||||
|
||||
/* Error codes */
|
||||
#define ECONN 1000 /* Tried to connect to already connected port */
|
||||
#define ETYPE 1001 /* Tried an operation on a cell that does not support it */
|
||||
#define ERECONF 1100 /* Tried to set a configuration bit to multiple values */
|
||||
|
||||
#endif // FPGA_GLOBAL_H
|
|
@ -0,0 +1,130 @@
|
|||
#include <stdio.h>
|
||||
#include "fpga_cell.h"
|
||||
#include "fpga_fdef_loader.h"
|
||||
#include "fpga_global.h"
|
||||
#include "fpga.h"
|
||||
#include "unistd.h"
|
||||
#include "string.h"
|
||||
|
||||
#include "fpga_cell_lut34.h" /* For testing purposes only */
|
||||
|
||||
#define E_FDEF 1
|
||||
#define E_BITSTREAM 2
|
||||
|
||||
static void test_design_cell_ripple(struct fpga_cell_lut34 *cell, int first, int last)
|
||||
{
|
||||
cell->lut_in_sel[0] = LUT_NET_F0; // Own state
|
||||
cell->lut_in_sel[1] = LUT_NET_F2; // Feedback &-net -- just for fun
|
||||
cell->lut_in_sel[2] = (first ? LUT_NET_T2 : LUT_NET_L1); // &-state of previous stages
|
||||
cell->lut_in_sel[3] = LUT_NET_L0; // Previous state -- just for fun
|
||||
cell->sync = 1;
|
||||
|
||||
cell->drive_sel[0] = 'A';
|
||||
cell->drive_sel[1] = 'b';
|
||||
cell->drive_sel[2] = (last ? 'b' : 'Z');
|
||||
cell->drive_sel[3] = 'Z';
|
||||
cell->route_en = (1 << ROUTE_L2);
|
||||
|
||||
cell->LUT3[0] = 0b01011010;
|
||||
cell->LUT3[1] = 0b10100000;
|
||||
}
|
||||
|
||||
// WARNING: Requires a >=4x4 FPGA FDEF!
|
||||
static void test_design_counter(struct fpga_cell *entry_cell)
|
||||
{
|
||||
struct fpga_cell_lut34 *cell;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < 4; ++i) {
|
||||
cell = ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]));
|
||||
for (j = 4 - i; j < 4; ++j) {
|
||||
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[BOTTOM];
|
||||
}
|
||||
test_design_cell_ripple(cell, 1, 0);
|
||||
|
||||
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
|
||||
test_design_cell_ripple(cell, 0, 0);
|
||||
|
||||
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
|
||||
test_design_cell_ripple(cell, 0, 0);
|
||||
|
||||
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
|
||||
test_design_cell_ripple(cell, 0, 1);
|
||||
}
|
||||
}
|
||||
|
||||
int development_test_main(int argc, char *argv[])
|
||||
{
|
||||
struct fpga_cell *entry_cell;
|
||||
struct fpga_chain *chain;
|
||||
|
||||
int opt;
|
||||
char *fdef_filename = "fdef/4x4.fdef";
|
||||
char *kst_filename = "-";
|
||||
char *bitstream_filename = "-";
|
||||
int bitstream_ascii = 0;
|
||||
|
||||
set_log_level(LL_DEBUG);
|
||||
|
||||
while((opt = getopt(argc, argv, "f:i:o:h")) != -1)
|
||||
{
|
||||
switch(opt)
|
||||
{
|
||||
case 'f':
|
||||
fdef_filename = optarg;
|
||||
break;
|
||||
case 'i':
|
||||
kst_filename = optarg;
|
||||
report(LL_WARNING, "Input not yet implemented.");
|
||||
break;
|
||||
case 'o':
|
||||
bitstream_filename = optarg;
|
||||
break;
|
||||
case 'h':
|
||||
bitstream_ascii = 1;
|
||||
break;
|
||||
case ':':
|
||||
case '?':
|
||||
printf("Usage: %s [-f fdef] [-i input.kst] [-o output.bin] [-h]\n"
|
||||
"Generate bitstreams for the TTL-FPGA.\n\n"
|
||||
"When INPUT or OUTPUT is -, read/write standard input.\n\n"
|
||||
" -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
|
||||
" -i\tKousaten input file, default stdin\n"
|
||||
" -o\tOutput file, default stdout\n"
|
||||
" -h\tGenerate output as ASCII HEX\n",
|
||||
argv[0]);
|
||||
return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
entry_cell = fpga_fdef_loader_load(fdef_filename);
|
||||
if (!entry_cell) {
|
||||
report(LL_CRITICAL, "Error loading FDEF.");
|
||||
return E_FDEF;
|
||||
}
|
||||
report(LL_INFO, "FDEF loaded.");
|
||||
|
||||
chain = fpga_isp_chain_new(entry_cell);
|
||||
if (!chain) {
|
||||
report(LL_CRITICAL, "Critical error during bitstream generation.");
|
||||
return E_BITSTREAM;
|
||||
}
|
||||
report(LL_INFO, "Chain loaded.");
|
||||
|
||||
test_design_counter(entry_cell);
|
||||
|
||||
if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) {
|
||||
report(LL_ERROR, "Bitstream generation failed.");
|
||||
return E_BITSTREAM;
|
||||
}
|
||||
report(LL_INFO, "Generated bitstream.");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
return development_test_main(argc, argv);
|
||||
}
|
Loading…
Reference in New Issue