|
|
e7d9f391ef
|
fpga: Clean up clocking code
|
2024-08-09 14:01:16 +02:00 |
|
|
|
b06ccdda2a
|
fpga: Update UART baud rate to 250 kbaud/s
|
2024-08-09 11:31:59 +02:00 |
|
|
|
876693ca5f
|
fpga: uart_wb: Latch received byte to allow late retrieval of data
Else, the CPU would get the part old / half current byte. This
enables boot loader baud rates in excess of 19200 baud.
|
2024-08-09 11:29:33 +02:00 |
|
|
|
49ccbea9e9
|
fpga: aps6404l device model: Remove unnecessary newlines
|
2024-08-01 21:11:47 +02:00 |
|
|
|
eddbcf5f6f
|
fpga: trashernet_phy_wb: Ensure LEDs blink even with constant traffic
|
2024-08-01 21:10:53 +02:00 |
|
|
|
74280fb79a
|
fpga: Implement single-instruction prefetching from external RAM
|
2024-08-01 21:06:14 +02:00 |
|
|
|
280b354813
|
fpga: aps6404l_controller: Add generic to select wrap mode
|
2024-08-01 21:03:12 +02:00 |
|
|
|
7bece90229
|
fpga: Cleanly separate build VUnit from bench VUnit
|
2024-08-01 21:02:32 +02:00 |
|
|
|
db5a14a2f0
|
fpga: Add generic FIFO core
|
2024-07-26 10:55:32 +02:00 |
|
|
|
e81166a82c
|
fpga: Implement functional Ethernet controller
|
2024-07-23 19:13:42 +02:00 |
|
|
|
79b1153df7
|
env: Makefile: Add support for icetime
|
2024-07-23 18:53:17 +02:00 |
|
|
|
0209a23980
|
fpga: Fix clock constraint for system clock
|
2024-07-23 18:52:14 +02:00 |
|
|
|
23c7d0ab20
|
env: run.py: Remove unnecessary files from compilation for synthesis
|
2024-07-07 15:58:32 +02:00 |
|
|
|
e1672bb712
|
fpga: Test Trashernet TX
|
2024-07-07 15:31:41 +02:00 |
|
|
|
434a06fa70
|
env: Replace build script with proper Makefile
|
2024-07-06 19:15:20 +02:00 |
|
|
|
dd7cf08b6f
|
fpga: Continue work on full HW support
|
2024-07-06 19:14:39 +02:00 |
|
|
|
b7c1286d76
|
fpga: Implement basic SERV SoC
|
2024-06-22 11:28:15 +02:00 |
|
