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01918678ce
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Add licensing information
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2019-06-06 20:45:55 +02:00 |
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8b80a78b3b
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Layout input muxing
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2019-06-05 23:32:39 +02:00 |
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b15d865090
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Start layout
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2019-06-04 22:43:08 +02:00 |
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a2608f41ae
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Ignore BOM
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2019-06-04 22:42:56 +02:00 |
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5bcc79e505
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Create copy of kicad design to optimize for layout
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2019-06-04 21:15:25 +02:00 |
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2c21b9191c
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Move kicad design into separate directory
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2019-06-04 21:14:25 +02:00 |
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798144c729
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Update global project config for PCBWay's rules
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2019-06-04 21:11:08 +02:00 |
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a62036545c
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Reannotate schematic
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2019-06-04 21:05:23 +02:00 |
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5ecdc8c13d
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Clean up
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2019-06-04 20:57:14 +02:00 |
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7b7d467935
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Add power LED and bulk capacitor
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2019-06-04 20:51:59 +02:00 |
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9eaef0c055
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Swap L and T bus on input MUX
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2019-06-01 22:42:13 +02:00 |
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104cc9c9c9
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Flip top and bottom connectors
That way, pin 1 is always left or top.
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2019-06-01 22:22:40 +02:00 |
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626dbde9fe
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Change input LUT mapping to allow F3 access in mode-3
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2019-06-01 22:03:01 +02:00 |
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f762348d03
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Fix footprint of U14
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2019-06-01 18:33:12 +02:00 |
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2c162e729b
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Fix DRC issues
Fixes #6.
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2019-06-01 18:31:45 +02:00 |
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6b2fa97a6f
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Fix right and bottom bus connections
Fixes #2.
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2019-06-01 18:20:26 +02:00 |
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76b1d2d01f
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Annotate, and assign preliminary parts
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2019-06-01 18:12:15 +02:00 |
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037d13c5f6
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Exchange fabric2 with fabric3 on input MUX 2
Resolves #1.
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2019-06-01 17:51:20 +02:00 |
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28b9ad42c3
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Change gender of right and bottom connector
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2019-05-31 22:19:01 +02:00 |
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5445fa2831
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Editorial
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2019-05-31 22:14:42 +02:00 |
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7066cd590e
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Force protection resistors at fabric driver outputs
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2019-05-31 22:12:15 +02:00 |
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e3c4a300d2
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Add pdf and plt to gitignore
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2019-05-31 21:59:20 +02:00 |
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a803213b37
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Replace mode select with schottky + negated
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2019-05-31 21:59:05 +02:00 |
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2a44b7d1c5
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Replace mode select transistor logic with NOR gates
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2019-05-31 21:06:05 +02:00 |
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9b3da0fd87
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Fix LUT3/4 selection logic
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2019-05-31 20:36:29 +02:00 |
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37c33e8200
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Include LUTD config in bit map
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2019-05-31 20:36:00 +02:00 |
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e66cd09c68
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Add LEDs
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2019-05-31 18:52:59 +02:00 |
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6cbafd76a3
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Implement PCB top level
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2019-05-31 18:06:53 +02:00 |
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d630a3ee84
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Redesign routing and input muxing
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2019-05-31 16:36:08 +02:00 |
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1f3df7f87c
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Add bypass caps and clean up a bit
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2019-05-30 21:36:22 +02:00 |
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bf55a828a8
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Fix LUT split enable logic
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2019-05-30 21:12:52 +02:00 |
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9be0ea5ed4
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Design first draft of core logic
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2019-05-30 20:24:33 +02:00 |
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