Commit Graph

20 Commits

Author SHA1 Message Date
Markus Koch 626dbde9fe Change input LUT mapping to allow F3 access in mode-3 2019-06-01 22:03:01 +02:00
Markus Koch f762348d03 Fix footprint of U14 2019-06-01 18:33:12 +02:00
Markus Koch 2c162e729b Fix DRC issues
Fixes #6.
2019-06-01 18:31:45 +02:00
Markus Koch 6b2fa97a6f Fix right and bottom bus connections
Fixes #2.
2019-06-01 18:20:26 +02:00
Markus Koch 76b1d2d01f Annotate, and assign preliminary parts 2019-06-01 18:12:15 +02:00
Markus Koch 037d13c5f6 Exchange fabric2 with fabric3 on input MUX 2
Resolves #1.
2019-06-01 17:51:20 +02:00
Markus Koch 28b9ad42c3 Change gender of right and bottom connector 2019-05-31 22:19:01 +02:00
Markus Koch 5445fa2831 Editorial 2019-05-31 22:14:42 +02:00
Markus Koch 7066cd590e Force protection resistors at fabric driver outputs 2019-05-31 22:12:15 +02:00
Markus Koch e3c4a300d2 Add pdf and plt to gitignore 2019-05-31 21:59:20 +02:00
Markus Koch a803213b37 Replace mode select with schottky + negated 2019-05-31 21:59:05 +02:00
Markus Koch 2a44b7d1c5 Replace mode select transistor logic with NOR gates 2019-05-31 21:06:05 +02:00
Markus Koch 9b3da0fd87 Fix LUT3/4 selection logic 2019-05-31 20:36:29 +02:00
Markus Koch 37c33e8200 Include LUTD config in bit map 2019-05-31 20:36:00 +02:00
Markus Koch e66cd09c68 Add LEDs 2019-05-31 18:52:59 +02:00
Markus Koch 6cbafd76a3 Implement PCB top level 2019-05-31 18:06:53 +02:00
Markus Koch d630a3ee84 Redesign routing and input muxing 2019-05-31 16:36:08 +02:00
Markus Koch 1f3df7f87c Add bypass caps and clean up a bit 2019-05-30 21:36:22 +02:00
Markus Koch bf55a828a8 Fix LUT split enable logic 2019-05-30 21:12:52 +02:00
Markus Koch 9be0ea5ed4 Design first draft of core logic 2019-05-30 20:24:33 +02:00