f57b0b1054
raw_mac: Implement MAC without header field en-/decoding (only CRC + framing)
2024-07-15 13:37:42 +02:00
7379df7b74
phy: Improve clock accuracy at 0.5 dividers at the cost of some jitter
2024-07-15 13:34:54 +02:00
21a0d0e69a
phy_cdc: Allow unlimited clock ratios
...
Actually, assuming that each clock domain is fast enough for 10 MBit/s,
there is no problem running crazy ratios.
2024-07-06 18:05:00 +02:00
943febcb99
phy_cdc: Fix synchronization behavior
...
For low ratios of the two clock domains, the slow clock domain would
receive incorrect data as the fast (PHY) clock domain's data output
would have already updated with the first bit of the next byte by
the time the slow (system) clock domain read it.
This fix registers the data in the source clock domain as opposed
to the destination clock domain. This is allowed because the valid
strobe is synchronized in a way to guarantee that data has been
valid for a while when it becomes asserted.
Additionally, `phy_out.rx_data` and `phy_out.rx_data_valid` are no
longer registered in the destination (system) clock domain as this
now introduces unnecessary latency. Also, this was broken the way
it was anyway as `rx_active` and `rx_error` would've also had to be
registered to keep all timings in sync.
2024-07-06 17:58:11 +02:00
da7e329939
des: Fix compatibility with Yosys
2024-06-22 11:19:02 +02:00
4bce111d69
doc: Add synthesized size for PHY-only design
2024-02-04 09:34:36 +01:00
2190f146a0
doc: Add IPv4 modules to doc
2022-11-01 17:41:39 +01:00
91cdb13bb3
demo: Add ICMP ping reply demo design
2022-11-01 17:39:39 +01:00
0db98483dc
ipv4: Change syntax to make Synplify happy
2022-11-01 17:10:33 +01:00
6de8d24537
icmp: Implement ICMP echo replies
2022-11-01 16:23:27 +01:00
87bc9ce3d7
ipv4: Add rx_length field
2022-11-01 16:22:59 +01:00
fdcb1cb719
ipv4: Implement IPv4 TX
2022-10-31 23:46:46 +01:00
a0c9df28f1
ipv4: Remove obsolete signals
2022-10-31 23:45:05 +01:00
0d7981f801
ipv4: Default sr to all zeroes to squelch warnings
2022-10-31 17:02:37 +01:00
172a11070b
ipv4prot: Implement IPv4 protocol muxing
2022-10-31 16:57:54 +01:00
9d9b3b1cce
eth: Fix incorrect TX exit condition
2022-10-31 16:56:17 +01:00
e421ba0dff
eth: Fix missing reset for tx sel
2022-10-31 16:55:13 +01:00
277d01737d
ipv4: Implement RX
2022-10-30 22:32:47 +01:00
a19de6d0c8
gen: Add generic timer module
2022-10-30 22:31:10 +01:00
1c08d48861
doc: Add ARP layer to README
2022-10-30 17:38:29 +01:00
ccb7d6c0da
Fix linter warnings
2022-10-30 17:29:14 +01:00
8d9ca9e784
arp: Rename timeout_tick to systick
2022-10-30 17:27:43 +01:00
3240f363ba
arp: Reformat code
2022-10-29 19:19:16 +02:00
a5d5ca280d
arp: Add timeout
2022-10-29 19:18:51 +02:00
651b6bb11e
bench: Test ARP requests in HWITL
2022-10-28 18:55:04 +02:00
4804674d8e
arp: Implement ARP requests
...
This is still missing timeout in case of no reply.
This needs to be added!
2022-10-28 18:52:17 +02:00
1a41120afa
bench: Clarify HWITL interface creation for local testing
2022-10-27 17:02:53 +02:00
5f7704cf63
pkg: Implement to_string functions for MAC and IP addresses
2022-05-15 14:51:52 +02:00
5f389b0c7b
arp: Implement ARP replies
2022-05-15 14:51:49 +02:00
7bb82a9acf
doc: Add trashernet_eth to documentation
2022-05-15 14:40:45 +02:00
3c1c14f953
bench: hw_itl: Add debug prints for RX/TX
2022-05-15 14:37:21 +02:00
50b65bccec
eth: tx: Remove accidental latch
2022-05-15 14:30:45 +02:00
461c7ebce1
eth: tx: Fix polarity of tx_active checks
2022-05-15 14:27:26 +02:00
eab8783c6b
bench: Disable wave logging by default
2022-05-13 21:03:12 +02:00
8f4e996d57
bench: Clean up HWITL bench
2022-05-13 20:42:18 +02:00
e420b08eb2
bench: Add preliminary HWITL test for eth core
2022-05-13 20:39:05 +02:00
7aa1b56bf9
eth: Add Ethernet type MUX
2022-05-13 20:37:28 +02:00
8f3420bd54
pkg: Add configuration_t to trashernet
2022-05-13 20:36:52 +02:00
4b4e5fdbfa
bench: hw_itl: Calculate and append FCS for incoming frames
2022-05-13 18:20:13 +02:00
0e80900426
bench: hw_itl: Add comments
2022-05-13 18:19:35 +02:00
fd721ae24f
bench: Move HWITL tests to own top level / test bench file
2022-04-30 12:53:35 +02:00
82d4e6808b
bench: hwitl: Fix design to HW comms
...
Forgot to remove the sync header.
2022-04-30 12:48:39 +02:00
1c281bc0f7
bench: Add hardware-in-the-loop test
2022-04-29 20:53:20 +02:00
c4f4cfe68e
bench: Allow for different bench top levels in Makefile
2022-04-29 20:52:31 +02:00
f224aee487
doc: Add licensing info about the components of the logo
2022-04-24 12:26:19 +02:00
f45ded2ca9
bench: Add cocotb-based test bench for MAC test
2022-04-18 17:06:53 +02:00
7d86f6a262
env: Add Sigasi project files
2022-04-18 10:17:42 +02:00
313711dbc0
doc: Add KiCad schematic
2022-04-18 10:04:24 +02:00
0f7437e901
demo: Fix missing record in mac demo
...
Will eventually become part of trashernet, I guess. But for now,
let's add it to the top level.
2022-04-18 09:44:27 +02:00
5c27b685dc
demo: Move top level to library work
...
With Diamond, the design top level *must* be in the "work" library,
otherwise your project will be haunted with weird compile errors
that sometimes simply cause the build to fail with an arbitrary
error message, but can sometimes even lead to a straight-up broken
bitstream.
Real bad stuff, so let's move the stuff from our "design" library
to "work". That fixes it.
2022-02-12 13:19:14 +01:00
