d75c373da7
Add support for Zephyr
...
Most of the basic SoC drivers are copied from the official SERV
source code and have only been adapted. This commit also adds
device tree files and other definitions to support the Trashernet
hardware.
A preliminary driver (polling-based) for the Trashernet Ethernet
module is also included.
2024-12-03 08:36:51 +01:00
b8f273c9b6
fpga: bench: Add bench to run larger programs from external RAM
2024-11-08 16:06:04 +01:00
9487f5c2ef
fpga: top: Refactor indentation
2024-11-08 15:52:46 +01:00
f21122c54b
fpga: Add script to remove $asserts from netlists
...
For some reason, GHDL adds some (not all) asserts to the
synthesis netlist. This script removes them.
2024-11-08 15:37:15 +01:00
0943656548
fpga: run.py: Increase NVC heap size to simulate full 8 MB of external RAM
2024-11-08 10:31:19 +01:00
4ca35ca18c
fpga: aps6404l device model: Print message instead of failing for out of bounds accesses
2024-11-08 10:29:07 +01:00
539d2e0908
fpga: aps6404l device model: Allow preloading memory from file
2024-11-08 10:28:54 +01:00
8cf103a18d
fpga: neorv32: Disable reset of regfile
2024-09-27 16:35:18 +02:00
cc4b088173
fpga: ram: Use Verilog model for synthesis and VHDL for simulation
2024-09-27 16:34:55 +02:00
7497f1f6bb
fpga: Add Sigasi / Code project
2024-09-27 14:47:45 +02:00
297d340d6a
fpga: bench: Add self-checking test bench for bootrom
2024-09-27 14:45:07 +02:00
ba299e537b
fpga: Add NEORV32 as alternative CPU core
2024-09-27 14:44:28 +02:00
bb7b2a7a10
fpga: servant_ram: Rewrite in VHDL
2024-09-27 14:42:38 +02:00
0545769bcd
fpga: bench: Fix top level clock pin name
2024-09-27 14:42:15 +02:00
3ecc6a4ed1
fpga: aps6404l_wb: Fix memory arbitration bug
2024-08-14 19:15:57 +02:00
838a8abe7b
tools: Update flasher script to new bus layout
2024-08-09 14:03:00 +02:00
e7d9f391ef
fpga: Clean up clocking code
2024-08-09 14:01:16 +02:00
b06ccdda2a
fpga: Update UART baud rate to 250 kbaud/s
2024-08-09 11:31:59 +02:00
876693ca5f
fpga: uart_wb: Latch received byte to allow late retrieval of data
...
Else, the CPU would get the part old / half current byte. This
enables boot loader baud rates in excess of 19200 baud.
2024-08-09 11:29:33 +02:00
e561c31691
sw: bootrom: Improve performance and reduce size
2024-08-07 18:01:22 +02:00
49ccbea9e9
fpga: aps6404l device model: Remove unnecessary newlines
2024-08-01 21:11:47 +02:00
eddbcf5f6f
fpga: trashernet_phy_wb: Ensure LEDs blink even with constant traffic
2024-08-01 21:10:53 +02:00
74280fb79a
fpga: Implement single-instruction prefetching from external RAM
2024-08-01 21:06:14 +02:00
280b354813
fpga: aps6404l_controller: Add generic to select wrap mode
2024-08-01 21:03:12 +02:00
7bece90229
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
db5a14a2f0
fpga: Add generic FIFO core
2024-07-26 10:55:32 +02:00
e81166a82c
fpga: Implement functional Ethernet controller
2024-07-23 19:13:42 +02:00
79b1153df7
env: Makefile: Add support for icetime
2024-07-23 18:53:17 +02:00
0209a23980
fpga: Fix clock constraint for system clock
2024-07-23 18:52:14 +02:00
23c7d0ab20
env: run.py: Remove unnecessary files from compilation for synthesis
2024-07-07 15:58:32 +02:00
07bac62438
tools: Add flash.py
2024-07-07 15:35:09 +02:00
e1672bb712
fpga: Test Trashernet TX
2024-07-07 15:31:41 +02:00
4057f5239e
sw: Add bootrom
2024-07-06 19:15:41 +02:00
434a06fa70
env: Replace build script with proper Makefile
2024-07-06 19:15:20 +02:00
dd7cf08b6f
fpga: Continue work on full HW support
2024-07-06 19:14:39 +02:00
c7caf2189b
doc: Add a copy of the MPL-2.0
2024-07-06 19:06:39 +02:00
b7c1286d76
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00
79c466ec50
Add licensing information
2024-06-02 10:30:26 +02:00
2f54996271
Swap RX+ and -
2024-06-02 10:15:13 +02:00
bdeff0d0ff
Design PCB
2024-06-01 12:23:16 +02:00