Commit Graph

41 Commits (9f96e5cf8243b4d1d5c6cf192679b6809da67cc5)

Author SHA1 Message Date
Markus Koch 9f96e5cf82 Editiorial 2019-06-13 19:19:26 +02:00
Markus Koch 01043be425 Remove incorrect junction
Fixes #7.
2019-06-13 19:18:58 +02:00
Markus Koch dc5b791b6d Finish layout 2019-06-13 19:16:26 +02:00
Markus Koch 339fb214d7 Continue work on rev 1 2019-06-11 21:50:54 +02:00
Markus Koch 1c6ae29a8f Layout rev 1 2019-06-10 19:48:44 +02:00
Markus Koch f85577c0f1 Reset routing, place all components 2019-06-10 17:27:15 +02:00
Markus Koch a1046d75b8 Continue trial layout 2019-06-10 14:25:54 +02:00
Markus Koch fc94685478 Every day I'm layoutin' 2019-06-09 23:22:42 +02:00
Markus Koch a9d8d0e654 doc: Add notes 2019-06-06 21:25:18 +02:00
Markus Koch 01918678ce Add licensing information 2019-06-06 20:45:55 +02:00
Markus Koch 8b80a78b3b Layout input muxing 2019-06-05 23:32:39 +02:00
Markus Koch b15d865090 Start layout 2019-06-04 22:43:08 +02:00
Markus Koch a2608f41ae Ignore BOM 2019-06-04 22:42:56 +02:00
Markus Koch 5bcc79e505 Create copy of kicad design to optimize for layout 2019-06-04 21:15:25 +02:00
Markus Koch 2c21b9191c Move kicad design into separate directory 2019-06-04 21:14:25 +02:00
Markus Koch 798144c729 Update global project config for PCBWay's rules 2019-06-04 21:11:08 +02:00
Markus Koch a62036545c Reannotate schematic 2019-06-04 21:05:23 +02:00
Markus Koch 5ecdc8c13d Clean up 2019-06-04 20:57:14 +02:00
Markus Koch 7b7d467935 Add power LED and bulk capacitor 2019-06-04 20:51:59 +02:00
Markus Koch 9eaef0c055 Swap L and T bus on input MUX 2019-06-01 22:42:13 +02:00
Markus Koch 104cc9c9c9 Flip top and bottom connectors
That way, pin 1 is always left or top.
2019-06-01 22:22:40 +02:00
Markus Koch 626dbde9fe Change input LUT mapping to allow F3 access in mode-3 2019-06-01 22:03:01 +02:00
Markus Koch f762348d03 Fix footprint of U14 2019-06-01 18:33:12 +02:00
Markus Koch 2c162e729b Fix DRC issues
Fixes #6.
2019-06-01 18:31:45 +02:00
Markus Koch 6b2fa97a6f Fix right and bottom bus connections
Fixes #2.
2019-06-01 18:20:26 +02:00
Markus Koch 76b1d2d01f Annotate, and assign preliminary parts 2019-06-01 18:12:15 +02:00
Markus Koch 037d13c5f6 Exchange fabric2 with fabric3 on input MUX 2
Resolves #1.
2019-06-01 17:51:20 +02:00
Markus Koch 28b9ad42c3 Change gender of right and bottom connector 2019-05-31 22:19:01 +02:00
Markus Koch 5445fa2831 Editorial 2019-05-31 22:14:42 +02:00
Markus Koch 7066cd590e Force protection resistors at fabric driver outputs 2019-05-31 22:12:15 +02:00
Markus Koch e3c4a300d2 Add pdf and plt to gitignore 2019-05-31 21:59:20 +02:00
Markus Koch a803213b37 Replace mode select with schottky + negated 2019-05-31 21:59:05 +02:00
Markus Koch 2a44b7d1c5 Replace mode select transistor logic with NOR gates 2019-05-31 21:06:05 +02:00
Markus Koch 9b3da0fd87 Fix LUT3/4 selection logic 2019-05-31 20:36:29 +02:00
Markus Koch 37c33e8200 Include LUTD config in bit map 2019-05-31 20:36:00 +02:00
Markus Koch e66cd09c68 Add LEDs 2019-05-31 18:52:59 +02:00
Markus Koch 6cbafd76a3 Implement PCB top level 2019-05-31 18:06:53 +02:00
Markus Koch d630a3ee84 Redesign routing and input muxing 2019-05-31 16:36:08 +02:00
Markus Koch 1f3df7f87c Add bypass caps and clean up a bit 2019-05-30 21:36:22 +02:00
Markus Koch bf55a828a8 Fix LUT split enable logic 2019-05-30 21:12:52 +02:00
Markus Koch 9be0ea5ed4 Design first draft of core logic 2019-05-30 20:24:33 +02:00