73 Commits

Author SHA1 Message Date
7a0da0f91d eth+ipv4prot: Fix protocol arbitration for real
The problem arises in the following scenario.

There are two sources: HIGH-prio and LOW-prio. Current selection
(from last transaction) is LOW-prio. This one completes.

Next, both request at the same time. Data and tx_en from LOW-prio is
latched -> first word is taken from there. Now, arbitration does its
job and switches to high prio. All acks and data go here.

Result: First byte is from LOW-prio source, rest is from HIGH-prio.

This commit fixes this behavior by resetting the selected channel to
the highest priority one, preventing the switch from pulling it away
from the selected one as the high priority is the one that will get
selected by the switching logic anyways.

Fixes #13.
2025-09-02 14:11:21 +02:00
f5b691fae5 Revert "eth+ipv4prot: Fix protocol arbitration"
This reverts commit 9258edd0d97ebcf924d81e2db2b9bdae0b9e575a.
We cannot just look at tx_en as there will be one more ack
strobe after its deassertion, which needs to get through to the
real source.

Reopens #13.
2025-09-02 12:46:28 +02:00
9258edd0d9 eth+ipv4prot: Fix protocol arbitration
Fixes #13.
2025-09-02 12:38:46 +02:00
f62a464e7e ipv4: Implement gateway handling
Closes #17.
2025-09-02 12:33:23 +02:00
f67e8d8b37 Reformat code using latest version of Sigasi 2025-09-02 09:45:30 +02:00
154604aacd udp: Add UDP decoder 2025-09-02 09:35:14 +02:00
02a00e875d ipv4: Implement tx_ok_stb 2025-09-02 09:31:38 +02:00
7379df7b74 phy: Improve clock accuracy at 0.5 dividers at the cost of some jitter 2024-07-15 13:34:54 +02:00
21a0d0e69a phy_cdc: Allow unlimited clock ratios
Actually, assuming that each clock domain is fast enough for 10 MBit/s,
there is no problem running crazy ratios.
2024-07-06 18:05:00 +02:00
943febcb99 phy_cdc: Fix synchronization behavior
For low ratios of the two clock domains, the slow clock domain would
receive incorrect data as the fast (PHY) clock domain's data output
would have already updated with the first bit of the next byte by
the time the slow (system) clock domain read it.

This fix registers the data in the source clock domain as opposed
to the destination clock domain. This is allowed because the valid
strobe is synchronized in a way to guarantee that data has been
valid for a while when it becomes asserted.

Additionally, `phy_out.rx_data` and `phy_out.rx_data_valid` are no
longer registered in the destination (system) clock domain as this
now introduces unnecessary latency. Also, this was broken the way
it was anyway as `rx_active` and `rx_error` would've also had to be
registered to keep all timings in sync.
2024-07-06 17:58:11 +02:00
da7e329939 des: Fix compatibility with Yosys 2024-06-22 11:19:02 +02:00
0db98483dc ipv4: Change syntax to make Synplify happy 2022-11-01 17:10:33 +01:00
6de8d24537 icmp: Implement ICMP echo replies 2022-11-01 16:23:27 +01:00
87bc9ce3d7 ipv4: Add rx_length field 2022-11-01 16:22:59 +01:00
fdcb1cb719 ipv4: Implement IPv4 TX 2022-10-31 23:46:46 +01:00
a0c9df28f1 ipv4: Remove obsolete signals 2022-10-31 23:45:05 +01:00
0d7981f801 ipv4: Default sr to all zeroes to squelch warnings 2022-10-31 17:02:37 +01:00
172a11070b ipv4prot: Implement IPv4 protocol muxing 2022-10-31 16:57:54 +01:00
9d9b3b1cce eth: Fix incorrect TX exit condition 2022-10-31 16:56:17 +01:00
e421ba0dff eth: Fix missing reset for tx sel 2022-10-31 16:55:13 +01:00
277d01737d ipv4: Implement RX 2022-10-30 22:32:47 +01:00
a19de6d0c8 gen: Add generic timer module 2022-10-30 22:31:10 +01:00
ccb7d6c0da Fix linter warnings 2022-10-30 17:29:14 +01:00
8d9ca9e784 arp: Rename timeout_tick to systick 2022-10-30 17:27:43 +01:00
3240f363ba arp: Reformat code 2022-10-29 19:19:16 +02:00
a5d5ca280d arp: Add timeout 2022-10-29 19:18:51 +02:00
4804674d8e arp: Implement ARP requests
This is still missing timeout in case of no reply.
This needs to be added!
2022-10-28 18:52:17 +02:00
5f7704cf63 pkg: Implement to_string functions for MAC and IP addresses 2022-05-15 14:51:52 +02:00
5f389b0c7b arp: Implement ARP replies 2022-05-15 14:51:49 +02:00
50b65bccec eth: tx: Remove accidental latch 2022-05-15 14:30:45 +02:00
461c7ebce1 eth: tx: Fix polarity of tx_active checks 2022-05-15 14:27:26 +02:00
7aa1b56bf9 eth: Add Ethernet type MUX 2022-05-13 20:37:28 +02:00
8f3420bd54 pkg: Add configuration_t to trashernet 2022-05-13 20:36:52 +02:00
61812c133f phy: Improve header synchronization 2022-01-30 19:26:43 +01:00
075f935e12 phy: Fix NLPs
We need a different NLP timeout for RX than TX.
Also use a prescaler to improve timing.
2022-01-29 20:15:02 +01:00
a9039a175c phy+mac: Improve interface
Instead of having the user wait until the en-low was latched by
the core, let's just latch it internally.
2022-01-23 16:52:05 +01:00
4a39c3d638 phy: Notify that the end-of-packet has been accepted 2022-01-23 16:31:20 +01:00
d1e0143c9d phy: Fix TX manchester encoding
Ethernet uses "inverted" manchester as per IEEE 802.3.
2022-01-23 16:02:31 +01:00
1bcddf4273 phy: Improve NLP timeout accuracy 2022-01-23 16:01:33 +01:00
afb545cd02 Clean up code formatting 2022-01-22 20:50:18 +01:00
4e39e3b371 phy: Do not report tx_active when providing NLPs 2022-01-22 20:48:49 +01:00
a2edc540b2 phy: Fix NLP timebase error 2022-01-22 20:48:23 +01:00
6f8bb7ba54 phy: Fix rounding error for NLP timeout 2022-01-22 20:47:47 +01:00
76eaff20fd mac+phy: Initialize all required variables 2022-01-22 20:47:09 +01:00
ef6b6378f8 mac: tx: Implement automatic padding
This also renames the bit_cnt signal to sr_cnt.
97d0905c08549e7e60a1d862360258f777dd5691 was kinda BS.

This fixes #4.
2022-01-16 14:44:43 +01:00
22b7d99b1f mac: Add tx_active output 2022-01-16 13:44:33 +01:00
97d0905c08 mac: Refactor incorrect signal name 2022-01-16 13:43:55 +01:00
10da238c60 mac: Refactor to use records for the application interface 2021-09-25 16:18:02 +02:00
cfac94136a phy: Refactor to use records for the application interface 2021-09-25 12:28:04 +02:00
cf6fb61195 mac: Use records for header fields 2021-09-25 12:19:54 +02:00