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5b54a596c1
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doc: Add circuit diagram
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2022-01-30 19:29:09 +01:00 |
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61812c133f
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phy: Improve header synchronization
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2022-01-30 19:26:43 +01:00 |
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075f935e12
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phy: Fix NLPs
We need a different NLP timeout for RX than TX.
Also use a prescaler to improve timing.
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2022-01-29 20:15:02 +01:00 |
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a9039a175c
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phy+mac: Improve interface
Instead of having the user wait until the en-low was latched by
the core, let's just latch it internally.
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2022-01-23 16:52:05 +01:00 |
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4a39c3d638
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phy: Notify that the end-of-packet has been accepted
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2022-01-23 16:31:20 +01:00 |
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d1150fb7db
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demo: Add MAC demo design
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2022-01-23 16:29:31 +01:00 |
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d1e0143c9d
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phy: Fix TX manchester encoding
Ethernet uses "inverted" manchester as per IEEE 802.3.
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2022-01-23 16:02:31 +01:00 |
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1bcddf4273
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phy: Improve NLP timeout accuracy
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2022-01-23 16:01:33 +01:00 |
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afb545cd02
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Clean up code formatting
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2022-01-22 20:50:18 +01:00 |
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4e39e3b371
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phy: Do not report tx_active when providing NLPs
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2022-01-22 20:48:49 +01:00 |
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a2edc540b2
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phy: Fix NLP timebase error
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2022-01-22 20:48:23 +01:00 |
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6f8bb7ba54
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phy: Fix rounding error for NLP timeout
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2022-01-22 20:47:47 +01:00 |
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76eaff20fd
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mac+phy: Initialize all required variables
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2022-01-22 20:47:09 +01:00 |
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37714d5c2d
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bench: Use VUnit
Well, not really. This just makes it compile and work with VUNIT,
but it's not a real VUnit test bench. Will do that at some other
point.
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2022-01-16 17:46:01 +01:00 |
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ef6b6378f8
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mac: tx: Implement automatic padding
This also renames the bit_cnt signal to sr_cnt.
97d0905c08 was kinda BS.
This fixes #4.
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2022-01-16 14:44:43 +01:00 |
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22b7d99b1f
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mac: Add tx_active output
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2022-01-16 13:44:33 +01:00 |
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97d0905c08
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mac: Refactor incorrect signal name
|
2022-01-16 13:43:55 +01:00 |
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18b4213ed0
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doc: Add Trashernet logo
|
2021-09-25 20:28:43 +02:00 |
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10da238c60
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mac: Refactor to use records for the application interface
|
2021-09-25 16:18:02 +02:00 |
|
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cfac94136a
|
phy: Refactor to use records for the application interface
|
2021-09-25 12:28:04 +02:00 |
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cf6fb61195
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mac: Use records for header fields
|
2021-09-25 12:19:54 +02:00 |
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9addd97b57
|
Rename types package to general trashernet package
|
2021-09-25 11:07:12 +02:00 |
|
|
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1bff61d24a
|
Fix code formatting
|
2021-09-04 19:33:44 +02:00 |
|
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743d2465d9
|
Add license headers
|
2021-09-04 19:33:32 +02:00 |
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35093bba85
|
bench: Test MAC TX
|
2021-09-04 19:15:45 +02:00 |
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2bee387081
|
mac: Implement TX path
|
2021-09-04 19:15:21 +02:00 |
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5a1363615f
|
bench: Update PHY ports
|
2021-09-04 19:14:42 +02:00 |
|
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29bbb50f6a
|
phy: tx: Fix TX startup handling
|
2021-09-04 19:09:04 +02:00 |
|
|
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9afdb984f9
|
phy: tx: Pass tx_n through the CDC wrapper
|
2021-09-04 19:08:42 +02:00 |
|
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13ef230503
|
phy: tx: Implement tx_active flag
|
2021-09-04 19:06:43 +02:00 |
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dcbd9675f6
|
phy: Use byte type for ports
|
2021-09-04 19:05:53 +02:00 |
|
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16026849e8
|
phy: tx: Implement transmitter
|
2021-08-31 20:36:35 +02:00 |
|
|
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6322f5a317
|
Add trashernet_types package
|
2021-08-31 20:35:15 +02:00 |
|
|
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3775dc336b
|
mac: Add MAC RX
|
2021-08-30 13:27:30 +02:00 |
|
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76301f0a97
|
bench: Add IPG after send_data
|
2021-08-30 13:27:03 +02:00 |
|
|
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1f353fcb2f
|
phy: rx: Do not reset rx_data to save resources
|
2021-08-30 13:26:46 +02:00 |
|
|
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355bbc5ab1
|
mac: Add generic CRC
|
2021-08-30 12:15:23 +02:00 |
|
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775024e91f
|
bench: Add basic test bench for PHY
|
2021-08-30 12:14:58 +02:00 |
|
|
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dddfdbabc1
|
phy: Add CDC wrapper
|
2021-08-28 19:09:14 +02:00 |
|
|
|
d16f1afd9a
|
phy: Rename rx/tx signals
|
2021-08-28 19:08:37 +02:00 |
|
|
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3900d454f9
|
misc: Allow dynamic length for synchronizer
|
2021-08-28 19:08:07 +02:00 |
|
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38f96cdc63
|
phy: rx: Come up in disconnected state after reset
|
2021-08-28 14:25:51 +02:00 |
|
|
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0133fa8cce
|
phy: rx: Fix bit order
|
2021-08-28 14:25:47 +02:00 |
|
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9e5b958f46
|
phy: rx: Reset transition analyzer state at the EOT
|
2021-08-28 14:24:28 +02:00 |
|
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f5f643287f
|
phy: rx: Cleanup
|
2021-08-28 14:23:44 +02:00 |
|
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1f894866ab
|
phy: rx: Implement error handling for Manchester
|
2021-08-28 14:23:15 +02:00 |
|
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5d6df0219b
|
phy: rx: Introduce simple glitch filter
|
2021-08-28 14:22:28 +02:00 |
|
|
|
08bd5f166b
|
Implement PHY RX
|
2021-08-27 20:14:19 +02:00 |
|
|
|
85f3a3021a
|
Initial commit
|
2021-08-27 20:10:47 +02:00 |
|
