f45ded2ca9
bench: Add cocotb-based test bench for MAC test
2022-04-18 17:06:53 +02:00
7d86f6a262
env: Add Sigasi project files
2022-04-18 10:17:42 +02:00
313711dbc0
doc: Add KiCad schematic
2022-04-18 10:04:24 +02:00
0f7437e901
demo: Fix missing record in mac demo
...
Will eventually become part of trashernet, I guess. But for now,
let's add it to the top level.
2022-04-18 09:44:27 +02:00
5c27b685dc
demo: Move top level to library work
...
With Diamond, the design top level *must* be in the "work" library,
otherwise your project will be haunted with weird compile errors
that sometimes simply cause the build to fail with an arbitrary
error message, but can sometimes even lead to a straight-up broken
bitstream.
Real bad stuff, so let's move the stuff from our "design" library
to "work". That fixes it.
2022-02-12 13:19:14 +01:00
6beb9c8346
demo: Remove wait state
...
Not needed since a9039a175c
2022-01-30 19:40:55 +01:00
5b54a596c1
doc: Add circuit diagram
2022-01-30 19:29:09 +01:00
61812c133f
phy: Improve header synchronization
2022-01-30 19:26:43 +01:00
075f935e12
phy: Fix NLPs
...
We need a different NLP timeout for RX than TX.
Also use a prescaler to improve timing.
2022-01-29 20:15:02 +01:00
a9039a175c
phy+mac: Improve interface
...
Instead of having the user wait until the en-low was latched by
the core, let's just latch it internally.
2022-01-23 16:52:05 +01:00
4a39c3d638
phy: Notify that the end-of-packet has been accepted
2022-01-23 16:31:20 +01:00
d1150fb7db
demo: Add MAC demo design
2022-01-23 16:29:31 +01:00
d1e0143c9d
phy: Fix TX manchester encoding
...
Ethernet uses "inverted" manchester as per IEEE 802.3.
2022-01-23 16:02:31 +01:00
1bcddf4273
phy: Improve NLP timeout accuracy
2022-01-23 16:01:33 +01:00
afb545cd02
Clean up code formatting
2022-01-22 20:50:18 +01:00
4e39e3b371
phy: Do not report tx_active when providing NLPs
2022-01-22 20:48:49 +01:00
a2edc540b2
phy: Fix NLP timebase error
2022-01-22 20:48:23 +01:00
6f8bb7ba54
phy: Fix rounding error for NLP timeout
2022-01-22 20:47:47 +01:00
76eaff20fd
mac+phy: Initialize all required variables
2022-01-22 20:47:09 +01:00
37714d5c2d
bench: Use VUnit
...
Well, not really. This just makes it compile and work with VUNIT,
but it's not a real VUnit test bench. Will do that at some other
point.
2022-01-16 17:46:01 +01:00
ef6b6378f8
mac: tx: Implement automatic padding
...
This also renames the bit_cnt signal to sr_cnt.
97d0905c08fixes #4 .
2022-01-16 14:44:43 +01:00
22b7d99b1f
mac: Add tx_active output
2022-01-16 13:44:33 +01:00
97d0905c08
mac: Refactor incorrect signal name
2022-01-16 13:43:55 +01:00
18b4213ed0
doc: Add Trashernet logo
2021-09-25 20:28:43 +02:00
10da238c60
mac: Refactor to use records for the application interface
2021-09-25 16:18:02 +02:00
cfac94136a
phy: Refactor to use records for the application interface
2021-09-25 12:28:04 +02:00
cf6fb61195
mac: Use records for header fields
2021-09-25 12:19:54 +02:00
9addd97b57
Rename types package to general trashernet package
2021-09-25 11:07:12 +02:00
1bff61d24a
Fix code formatting
2021-09-04 19:33:44 +02:00
743d2465d9
Add license headers
2021-09-04 19:33:32 +02:00
35093bba85
bench: Test MAC TX
2021-09-04 19:15:45 +02:00
2bee387081
mac: Implement TX path
2021-09-04 19:15:21 +02:00
5a1363615f
bench: Update PHY ports
2021-09-04 19:14:42 +02:00
29bbb50f6a
phy: tx: Fix TX startup handling
2021-09-04 19:09:04 +02:00
9afdb984f9
phy: tx: Pass tx_n through the CDC wrapper
2021-09-04 19:08:42 +02:00
13ef230503
phy: tx: Implement tx_active flag
2021-09-04 19:06:43 +02:00
dcbd9675f6
phy: Use byte type for ports
2021-09-04 19:05:53 +02:00
16026849e8
phy: tx: Implement transmitter
2021-08-31 20:36:35 +02:00
6322f5a317
Add trashernet_types package
2021-08-31 20:35:15 +02:00
3775dc336b
mac: Add MAC RX
2021-08-30 13:27:30 +02:00
76301f0a97
bench: Add IPG after send_data
2021-08-30 13:27:03 +02:00
1f353fcb2f
phy: rx: Do not reset rx_data to save resources
2021-08-30 13:26:46 +02:00
355bbc5ab1
mac: Add generic CRC
2021-08-30 12:15:23 +02:00
775024e91f
bench: Add basic test bench for PHY
2021-08-30 12:14:58 +02:00
dddfdbabc1
phy: Add CDC wrapper
2021-08-28 19:09:14 +02:00
d16f1afd9a
phy: Rename rx/tx signals
2021-08-28 19:08:37 +02:00
3900d454f9
misc: Allow dynamic length for synchronizer
2021-08-28 19:08:07 +02:00
38f96cdc63
phy: rx: Come up in disconnected state after reset
2021-08-28 14:25:51 +02:00
0133fa8cce
phy: rx: Fix bit order
2021-08-28 14:25:47 +02:00
9e5b958f46
phy: rx: Reset transition analyzer state at the EOT
2021-08-28 14:24:28 +02:00
